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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Mon Apr 20, 2015 5:14 pm 
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Joined: Tue Dec 02, 2008 9:42 am
Posts: 42
My own patch of Bubble Bobble ran perfectly on my 060. It should still be available on Aminet.


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Tue Apr 21, 2015 8:43 pm 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1566
Location: .de
Kick 1.2 should be used as the lowest limit for games and demos.
Some title only work with this version and others require V1.3.

Kick 1.0 and 1.1 are not advisable since they have no fast/slow RAM detection and only know of 512kb of chip RAM.
Even the Kick 1.2 release without the "V1.2" lable act differently, at least for the game "Test Drive" ;)

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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Thu Apr 23, 2015 2:19 pm 
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Posts: 6
Yeah, I've got a bit of Amiga (re-)learning, with over 20 years of absence since I did the mistake of selling my Amiga 500 to buy a 386 ;)

Anyway, I spent the last couple of evenings improving the host (i.e. the openrisc cpu) interface to the SDRAM.
First I had an idea of replacing the SDRAM controller completely with a high-performing one I wrote a couple of
years ago (https://github.com/skristiansson/wb_sdram_ctrl), but after some proof-of-concept test I came to
the conclusion that even though it's well performing, it's way too indeterministic to be able to ensure
a response within the 16 cycles on the 114 MHz clock.

So, instead, I made improvements to the existing SDRAM controller.
The changes I made was to make the host interface 32-bit instead of 16-bit.
This was possible by caching the (4 16-bit word) burst data on reads, and
change settings of the SDRAM to perform write bursts.
On the write bursts I control the dqm signals on the two (of four) first accesses for
the host interface and the first access for chip/cpu accesses.
On the remaining two accesses I tie the dqm signals high (i.e. these accesses are always no-ops).

The result is slightly improved numbers in sysinfo.
(And I can now run moonstone with fastram enabled, not sure if it's related or not).

Before:

Image
Image

After:

Image
Image


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Mon Sep 26, 2016 2:00 pm 
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Joined: Sun Sep 25, 2016 4:05 pm
Posts: 29
stekern wrote:
Another lacking feature of the DE0 Nano is that there is no SRAM, so the openrisc control cpu core has to share the SDRAM with minimig/tg68k
for it's main memory.
I mapped the upper 16MB of the SDRAM for the openrisc control cpu to use.

Hello!

Trying to build your DE0 Nano port.
Quartus TimeQuest reporting warning - timing requrements does not meet for TG68K processor`s 114 MHz clock.
This is just normal, am I right?
As this clock being gated inside the processor?

I am very beginner in the verilog, but vhdl is a complete darkness for me.
So how the TG68K works is beyond my understanding...

The fact that SRAM memory is used by host controller only is very helpful.
I`am planning to port minimig to Terasic DE1-SoC board, which does not have any SRAM.

But placing the host controller code also in SDRAM might impact the other hardware speed?
So the purpose of using SRAM was to unload SDRAM memory bus?
It seems that earlier releases of minimig-de1 port does not use SRAM.


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Mon Sep 26, 2016 5:00 pm 
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Joined: Tue Dec 13, 2011 7:48 pm
Posts: 341
sonycman wrote:
Trying to build your DE0 Nano port.
Quartus TimeQuest reporting warning - timing requrements does not meet for TG68K processor`s 114 MHz clock.
This is just normal, am I right?


Yes - it's not good, but it's normal for the TG68-based variants of the Minimig core.

Quote:
As this clock being gated inside the processor?


Nearly - there's an enable signal which is used to allow the CPU to run only on particular cycles. As I understand it an actual gated clock is where you prevent the clock signal itself from reaching the logic, rather than making its operation conditional upon an extra signal. Using an actual gated clock in an FPGA-based design is widely considered to be a Bad Idea.

Quote:
But placing the host controller code also in SDRAM might impact the other hardware speed?
So the purpose of using SRAM was to unload SDRAM memory bus?
It seems that earlier releases of minimig-de1 port does not use SRAM.


The Turbo Chameleon 64 port of minimig doesn't use SRAM either - because it doesn't have any. The MIST doesn't either - but it has an external microcontroller that runs the OSD and disk emulation.

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~ Amiga 4000/030 ~ Amiga 1200 030/50MHz ~ Turbo Chameleon 64 ~ Altera DE1 with Minimig core ~
Details of my projects: http://retroramblings.net


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Mon Sep 26, 2016 5:49 pm 
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Joined: Sun Sep 25, 2016 4:05 pm
Posts: 29
MMrobinsonb5 wrote:
Quote:
But placing the host controller code also in SDRAM might impact the other hardware speed?
So the purpose of using SRAM was to unload SDRAM memory bus?
It seems that earlier releases of minimig-de1 port does not use SRAM.


The Turbo Chameleon 64 port of minimig doesn't use SRAM either - because it doesn't have any. The MIST doesn't either - but it has an external microcontroller that runs the OSD and disk emulation.

I does not have the SRAM on DE1-SoC either - so the idea to use only SDRAM and FPGA is what i like!

Thank you for helping me, such a big project as the minimig port is very hard for me to understand, my head just boiling these days... :)

There is another question that bothers me.
As Stefan (topic starter) says:
Quote:
I mapped the upper 16MB of the SDRAM for the openrisc control cpu to use.

He had divided the SDRAM in two parts, to prevent CPUs overlap.
He did it in sdram controller instance, I presume:
Code:
//// sdram ////
sdram_ctrl sdram (
  // sys
  .sysclk       (clk_114          ),
  .c_7m         (clk_7            ),
  .reset_in     (sdctl_rst        ),
  .cache_rst    (tg68_rst         ),
  .reset_out    (reset_out        ),
  .cache_ena    (1/*cctrl[0]*/    ),
  // sdram
  .sdaddr       (DRAM_ADDR        ),
  .sd_cs        (sdram_cs         ),
  .ba           (sdram_ba         ),
  .sd_we        (DRAM_WE_N        ),
  .sd_ras       (DRAM_RAS_N       ),
  .sd_cas       (DRAM_CAS_N       ),
  .dqm          (sdram_dqm        ),
  .sdata        (DRAM_DQ          ),
  // host
  .host_cs      (bridge_cs        ),
  .host_adr     ({~bridge_adr[22], 2'b00, bridge_adr[21:0]}),
  .host_we      (bridge_we        ),
  .host_bs      (bridge_sel       ),
  .host_wdat    (bridge_dat_w     ),
  .host_rdat    (bridge_dat_r     ),
  .host_ack     (bridge_ack       ),
  // chip
  .chipAddr     ({2'b00, ram_address[21:1]}),
  .chipL        (_ram_ble         ),
  .chipU        (_ram_bhe         ),
  .chipRW       (_ram_we          ),
  .chip_dma     (_ram_oe          ),
  .chipWR       (ram_data         ),
  .chipRD       (ramdata_in       ),
  // cpu
  .cpuAddr      (tg68_cad[24:1]   ),
  .cpustate     (tg68_cpustate    ),
  .cpuL         (tg68_clds        ),
  .cpuU         (tg68_cuds        ),
  .cpu_dma      (tg68_cdma        ),
  .cpuWR        (tg68_dat_out     ),
  .cpuRD        (tg68_cout        ),
  .enaWRreg     (tg68_enaWR       ),
  .ena7RDreg    (tg68_ena7RD      ),
  .ena7WRreg    (tg68_ena7WR      ),
  .cpuena       (tg68_cpuena      )
);

In line 559 of the top module I see:
.host_adr ({~bridge_adr[22], 2'b00, bridge_adr[21:0]}),
MSB of the address inverted and forms 16MBytes offset.

But in the bootrom code host loads its firmware (DE1_BOOTBIN) to the RAM address of 0x400000.
And if bridge_adr will be equal to 0x400000, the hdl code above just inverts it to zero, and firmware will be loaded to zero address, in chip RAM, if I`am understand correctly!

Why bother inverting the incoming bridge_adr[22], and not just set its MSB constantly to 1'b1??

PS: sorry for bad english, its not easy for me to write in it :(


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Mon Sep 26, 2016 6:56 pm 
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Joined: Sun Sep 25, 2016 4:05 pm
Posts: 29
Compared sdram controllers of minimig-de1 (8 MBytes chip) and minimig-de0-nano (32 MBytes chip) and there is not much difference.
Just added one extra bit of address for RAS and CAS writes.

Is it really so easy to move from one SDRAM memory to another?

The DE1-SoC board has 64 Mbytes SDRAM chip, so I need to add another extra address bit and that is it?


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Mon Sep 26, 2016 11:51 pm 
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Joined: Tue Dec 13, 2011 7:48 pm
Posts: 341
sonycman wrote:
Is it really so easy to move from one SDRAM memory to another?

The DE1-SoC board has 64 Mbytes SDRAM chip, so I need to add another extra address bit and that is it?


Basically, yes. Just be aware that when the number of row bits increases, you might need to increase the number of refresh cycles.

If the SDRAM controller does anything clever with bank interleaving then you'll need to be careful about which address bits you map to the extra address bits, too. (Not an issue for the de0 Minimig port, but something to be aware of for other projects.)

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~ Amiga 4000/030 ~ Amiga 1200 030/50MHz ~ Turbo Chameleon 64 ~ Altera DE1 with Minimig core ~
Details of my projects: http://retroramblings.net


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Tue Sep 27, 2016 1:44 am 
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Joined: Sun Sep 25, 2016 4:05 pm
Posts: 29
MMrobinsonb5 wrote:
Basically, yes. Just be aware that when the number of row bits increases, you might need to increase the number of refresh cycles.

If the SDRAM controller does anything clever with bank interleaving then you'll need to be careful about which address bits you map to the extra address bits, too. (Not an issue for the de0 Minimig port, but something to be aware of for other projects.)

It seems that SDRAM controller used in de1\de0 ports is some kind of a simplified one - it lacks even refresh counter to modify.
It automatically runs refresh cycle if its state machine in idle state.

There is nothing unusual in the banks side also.

And the very chips is about to identical, differs only in memory size.

So I am just to add one column address bit and move to DE1-SoC board.

Thanks!

PS: now my little de0-nano board (without sd-card or vga dac connected) simply flashes error leds, indicating absence of sd-card.
Interesting - in it state it outputs some kind of video signal?

So it makes sence for me to solder some resistors and VGA DB-15 connector to check it hardware actually works or not?


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 Post subject: Re: minimig-de1 on DE0 Nano
PostPosted: Wed Sep 28, 2016 4:22 am 
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Joined: Sun Sep 25, 2016 4:05 pm
Posts: 29
Got some progress with de0-nano board - system booted from sdcard and finally lights up a single led (system status = 0x1), i.e. kickstart loaded?

But with de1-soc problems arised.
Board lights up four leds (status = 0xf) and thats it, no further changes, no flashes...
Does this mean mor1x controller hung up?
There is even no sdram involved at this stage, only rom code executed.

Thinking about to use Signal Tap and see, what is going on, but i did not even have disassembled boot rom code, only raw binary file for it.
If someone would be so kind to objdump it, so i could see which command actually executed...


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