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Discussing the Open Source FPGA Amiga Project
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 Post subject: Re: Huge problems with new DE-1
PostPosted: Tue Dec 17, 2013 10:36 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
Can you try this please:

http://www.krajnc.org/files/minimig-de1 ... sting2.zip

These are just the programming files. The serial output will not work, unfortunately, because I changed the frequency of the control block, but I forgot to recalculate the uart dividers ... and I'm too tired to do it again today ;)

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 Post subject: Re: Huge problems with new DE-1
PostPosted: Tue Dec 17, 2013 11:35 pm 
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Posts: 341
I believe there's a question mark over the SRAM on newer DE1s - if this is the problem it would explain why an early build worked, since (if memory serves correctly) the SRAM wasn't used by Minimig until Chaos's integration of the OR1200 CPU?

Some information scattered throughout this thread: http://atariage.com/forums/topic/213827 ... re/page-10

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 Post subject: Re: Problems with new DE-1
PostPosted: Tue Dec 17, 2013 11:38 pm 
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Joined: Sun Dec 15, 2013 3:43 pm
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Location: West Somerset, UK
Well done! That's really not far off.

With the debug de1_boot.bin I couldn't boot at all, but with the de1_boot.bin from the previous re6b2 release I can now reliably get to the kick screen every time. That may have been what you meant to do anyway!

OK, so the reason I say it's damn close is that if I try to go left or right in the OSD, it crashes and resets the Amiga. I can quite happily do everything within that first screen of the OSD however, so I just quite happily played a game of Alien Breed. I'm not sure if there were minor graphic glitches in that game or not. I need to compare to my real A600 which I'll do late tomorrow night - I'm tired too right now :)

Thank you VERY much for your efforts. It's hugely appreciated. As a developer I know what a pain it can be when over time you need to do a tweak here and a tweak there because of variations you've not seen or come across before.


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 Post subject: Re: Problems with new DE-1
PostPosted: Tue Dec 17, 2013 11:51 pm 
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Location: West Somerset, UK
That's an interesting read on the SRAM. I'd already heard of SRAM problems from someone on FaceBook (Ash - I don't think he's on here...)

However, I think (hope!) I'm right in saying that they're talking about SRAM manufactured by "EDBLL" whereas mine is by ISSI.

So like I say, hopeful faulty RAM is not the cause here.

I have also seen a comment by Ash on Mikes Spectrum core about getting very odd behaviour if the "Power-Up Don't Care" option is ticked. On that core I get graphic glitches galore, however it does run. I haven't got round to rebelling that core without that option selected yet. Something else on my "TODO" list :)


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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 12:51 am 
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MartinW wrote:
However, I think (hope!) I'm right in saying that they're talking about SRAM manufactured by "EDBLL" whereas mine is by ISSI.


Don't want to worry you, but EDBLL isn't the manufacturer - it's part of the ISSI part number: IS61WV25616EDBLL
My DE1 and DE2 both have IS61LV25616AL SRAMs, and someone whose board has an IS61WV25616BLL says that also seems to work OK.

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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 1:05 am 
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Oops! So it is. I guess if it just turns out to be different then there's not much i can do. If it's faulty, like two of the boards discussed in that other thread however then it goes back. It's only a week old so shouldn't be a problem. Proving it ay be another matter I guess.


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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 10:05 am 
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MartinW wrote:
With the debug de1_boot.bin I couldn't boot at all, but with the de1_boot.bin from the previous re6b2 release I can now reliably get to the kick screen every time. That may have been what you meant to do anyway!

OK, this is what I think is going on: that debug firmware build divides the SPI clock, so it is not running at full speed. Unfortunately there is a problem that I was sure was going to bite us in the ass someday - the SPI link between the control block and minimig is running on two different, non-aligned clocks, and the SPI bus is not completely properly handled for clock domain crossing. It only (more or less) works if the SPI master is faster - in a certain range - from the slave.
What I did for this last FPGA build is reduce the SRAM controller and control block clock from 100MHz/50MHz to 80MHz/40MHz, as that seemed (from your serial output) as a possible cause of the problems (spurious resets of the control CPU). The default clock of 100MHz actually requires that the SRAM is slightly faster than 100MHz because of the delay from the FPGA core to the IO pins and through the board to the SRAM.
That is why the debug firmware build is not working - since the SPI clock is derived from the ctrl clock, when divided it became less than 7MHz. The not-completely-working clock domain crossing could also be a problem why the OSD isn't working 100% for you for the normal firmware build.

MMrobinsonb5: thanks for reporting the same problems from the atariage forum. Although I can hardly believe it, this could indeed be a faulty SRAM chip (but come on, they have been making the same SRAM for years and years, in an old process technology, they should be close to 0 errors by now! :) Perhaps bad waffers, or a small change that wasn't tested ...).
Tobiflexx' builds did use the SRAM, it was used for the HDD buffers if I'm not mistaken. I think it was running at a much lower clock, though - probably 28MHz.
Can you please report any new findings from the atariage forums?

MartinW: I'm not sure what else I can do at the moment, but you could try running the Spectrum core for the DE1 or the cores from atariage to see if any of them has similiar problems. Unfortunately I don't have any experience with any of the mentioned cores. You could also try the default core from Terasic, together with the DE1 control panel - I think there is a SRAM test there.

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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 10:29 am 
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Thanks for the good explanation, even if it's not such good news! There won't be any progress this evening I don't think as I'm out but I will do the SRAM test in the Terasic core and report back. I already tried the Spectrum core and while it worked it had a fair bit of corruption. Apparently setting the option that I spoke about earlier and re-building fixes that but I haven't had a chance to rebuild yet. Again, I will do and report back.

Thanks again, Martin.


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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 12:49 pm 
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chaos wrote:
MartinW: I'm not sure what else I can do at the moment, but you could try running the Spectrum core for the DE1 or the cores from atariage to see if any of them has similiar problems.


If it's just a matter of timing, would it be possible to restore the control / SRAM controller clock to what it was before, then just add some wait states in the SRAM controller, making it effectively 50MHz - or does the control block assume that it has zero-wait-state RAM at its disposal? Alternatively, maybe an 84MHz clock aligned with the chipset core's clock?

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Details of my projects: http://retroramblings.net


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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 12:54 pm 
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From my point of view, the thing I'm most keen to do (somehow!) is prove if my unit is defective, or if this is simply an unfortunate evolution of the product issue. Obviously being only a week old I still have plenty of scope for sending it back. Not sure how I go about that just yet. My first step is clearly to familiarise myself with rebuilding and optimising in the Quartus software because everything I've done to date (not much admittedly) has been using the Xilinix products. That was another reason for buying the DE-1 as it goes, to see what things were like on the other side of the fence so to speak :)


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