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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 1:31 pm 
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Joined: Sun Dec 15, 2013 3:43 pm
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Location: West Somerset, UK
When you guys with working units get a minute, could you confirm the SRAM part numbers that you know work. Ta.

If it's simply a case of replacing the SRAM with a known working variant then that's tempting...

My flash is slower too incidentally (90ns rather than 70ns), but minimill doesn't use it.


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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 1:37 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
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I took another look at the datasheets of the working and non-working SRAM chips, and there actually are some differences, namely the non-working SRAM is slower:
- /OE access time, 4.5ns vs 4ns
- /LB, /UB access time, quite slower, 6.5ns vs 4ns
There could also be an issue with the "Address is valid prior to or coincident with CE LOW transition", as the SRAM controller just changes both address and control signals at the same time, but so far, this has worked for any SRAM I ever worked with. There's no way to be sure, but to check it with a scope - if it is not working, the proper memory location will be read with 2x tAA time delay instead of 1x tAA.

So I guess this is reason enough to try your suggestion, MMrobinsonb5. I will try to update the SRAM controller with stretched accesses, asserting the address first and the control signal in the next cycle. But unfortunately this will probably have to wait until next week, or maybe after New Year.

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 Post subject: Re: Problems with new DE-1
PostPosted: Wed Dec 18, 2013 2:57 pm 
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Location: West Somerset, UK
No worries. I'll load the code up and have a nose as well when I get the time but I suspect it will take me a while to get my head around.

Thanks so far of course :)


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 Post subject: Re: Problems with new DE-1
PostPosted: Thu Dec 19, 2013 1:00 pm 
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Location: West Somerset, UK
I was having a look at the code for this and the Spectrum core last night. I only had time for a brief look. The minimig code is vastly more complex than I currently understand, but I also looked at the code for Mike Stirling's Spectrum core. That core also crashes and has graphic glitches etc.

It looked to me like /OE and /CE were permanently low in that project. If that's correct then that can't possibly comply to the "address must be valid prior to or coincident to /CE going low". However despite trying a few things I wasn't able to get it to do anything other than make things worse. So that does mean I may not be following what's going on in that project properly. That core also has the added complication of using the flash for it's ROMs and we know that these newer boards also have a slower 90ns flash rather than the 70ns one found in older boards.

Such a pain when manufacturers do this over time. Presumably nothing more than cost saving but who knows!


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 Post subject: Re: Problems with new DE-1
PostPosted: Thu Dec 19, 2013 1:51 pm 
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MartinW wrote:
It looked to me like /OE and /CE were permanently low in that project. If that's correct then that can't possibly comply to the "address must be valid prior to or coincident to /CE going low".


SRAM can be controlled in different ways, one is with /CE, another is with address, another is with /LB & /UB, ...
So it is OK to leave /OE and /CE low and just change the address and /LB /UB /WE. That statement about address being stable is only valid for the /CE control, if you don't use /CE ( = /CE tied low), you don't have to worry about it.

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 Post subject: Re: Problems with new DE-1
PostPosted: Thu Dec 19, 2013 2:00 pm 
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Location: West Somerset, UK
Ah, OK. I did wonder about the different modes that were listed in the data sheet!

If it's more down to pure timing then, and he fact that the chip is slower in certain aspects then it's beyond my very limited knowledge at present as I only know about literally adding delays in code with '#''s. And I'm guessing that's far too crude :)

[EDIT] I will continue to have a look at the Spectrum core though. It's considerably simpler and does make quite a bit of sense to me so it's likely I might be able to do something with that. Unless of course the RAM chip is simply faulty. But while it's possible they've had a bad batch it seems a bit unlikely.


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 Post subject: Re: Problems with new DE-1
PostPosted: Thu Dec 19, 2013 4:14 pm 
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I wonder if adding some timing constraints to the SRAM pins would help?

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 Post subject: Re: Problems with new DE-1
PostPosted: Thu Dec 19, 2013 5:16 pm 
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That thought had occurred to me, but I don't see a 'ucf' file in Quartus like there is in ISE. So I was a bit clueless as to where to look.


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 Post subject: Re: Problems with new DE-1
PostPosted: Thu Dec 19, 2013 5:49 pm 
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MartinW: Quartus uses SDC files (Synposis Design Constraints), vs. the Xilinx UCF files. BTW, I think Xilinx switched to SDC a while ago, too.

MMrobinsonb5: it might at least help to constraint the SRAM, so Timequest will report any timing violations, but it won't necessarily fix the timing problems with these new SRAMs. Besides, constraining SRAM is PITA, because of all the different control modes, especially the address one - you have to constraint every address pin separately.
The registers driving the pins could also be moved to the I/O regs, but I think that will only make it worse timing-wise. I added the required options to the qsf file, but I didn't enable/test them.

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 Post subject: Re: Problems with new DE-1
PostPosted: Sun Dec 29, 2013 2:44 pm 
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Hi MartinW,

here is another test version with stretched SRAM cycles, please try it and report if it helps. These are just the programming files, use the original or debug build of firmware on SD card.

http://www.krajnc.org/files/minimig-de1 ... sting3.zip

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