CHAOS....Not sure if this should be a new topic...but talking about disk access and R/W.... you know that IDEFIX upgrade that you can get for your A1200 that fits over the GARY chip, I think...it allows for PIO Mode 5...upto 15MB per sec maybe...not sure...I wonder if that logic could be added to the minimig.
I don't know the details of how the Idefix Express works, but I'm guessing it provides buffering for the IDE bus and allows tighter IDE cycle times, which is basically what the PIO modes specify. I'd say you are still limited with Gayle's bus speed to memory. Plus, since this is Programmed I/O, the CPU more or less directly drives the data transfers, so the achievable speed is greatly dependent on the CPU speed.
There is no actual IDE bus in minimig, all transfers are done over the SPI bus and the IDE registers are emulated, so I don't think that anything much can be done here. Well, except writing a DMA IDE controller, but that would require a new driver (scsi.device), and I have nowhere near enough knowledge atm. to write such a driver.
Right now, I only get about 900KB/sec on the minimig DE1 port...is that what every else is getting? Have to somehow figure out how to reverse engineer it...what logic is it taking over during operation...is it a complete redesign of the Gary chip...implementing all functions but just hijacking all of the on board GARY pins....
Yes, that speed is generally what is expected. The theoretical maximum frequency for SD cards with SPI bus is 25MHz, that means 25Mbit/s or a little under 3MB/s. Even with a perfect master, that speed is not achievable on real hardware. But there are things that can be done to increase the speed:
- get as fast SD card as you can find (although mostly all SD cards work at the same 25MHz frequency, there is a difference between them in what kind of delays they need between commands)
- increase the size of buffers in FPGA (as reading multiple blocks is much more efficient, a small increase in speed)
- instead of SPI bus use the 4-bit SD bus (this would require a compatible ARM controller & writing of a SD bus implementation in FPGA, would theoretically provide up to 4x speed increase)
- get (write!
) a faster CPU for the Amiga - as described earlier, the transfer speed is greatly dependent on the CPU speed (unfortunately, there are no plans for a new, faster 68k FPGA core that I know of; however I am already - slowly! - working on a 68040-68060 type CPU for the minimig, but it will probably take me at least a year for any usable results, if I'll be able to do it at all)
- DMA IDE interface (would have to be written, but it is possible that yaqube has done something like that, if I read between the lines correctly