Master of Gizmo wrote:
It seems to me the chameleon code already has another port to the SDRAM as the second TG68 also uses the same physical SDRAM for its own purposes.
The second TG68 does have its own route into the SDRAM controller (the ports marked with a z prefix)
Actually this second TG68 might already be able to directly write into that portion of SDRAM which is used to store the kick.rom etc. Is this right?
There's currently some address mangling going on to keeps its address space separate from the first CPU. (If memory serves it's mapped to 0xA00000 on Chameleon, though I might have changed that in my most recent build, I'll have to check later.)
There's no reason why the second TG68 couldn't upload the ROM directly into the SDRAM, though the address mangling (which I think happens in the SDRAM controller module) may need adjusting. (I can't remember off the top of my head whether it's done with masking or bit toggling. If the latter, it's just a matter of figuring out the correct address to write to.)