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Discussing the Open Source FPGA Amiga Project
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 Post subject: New minimig build for the DE1
PostPosted: Fri Dec 30, 2011 2:52 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
I posted a new minimig build for the de1 with the latest minimig & tg68
sources on the minimigtg68 mailing list.

http://gamesource.groups.yahoo.com/group/minimigtg68/

If anyone is willing to give it a test drive, I'd appreciate it. It is in a more
or less working state, only keyboard joystick emu is still not working ok.

Happy holidays, enjoy!

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 Post subject: Re: New minimig build for the DE1
PostPosted: Mon Jan 02, 2012 12:37 pm 
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Joined: Sun Dec 28, 2008 3:00 pm
Posts: 59
Works fine here. Thank you very much.
Could you upload the sources, too ?

Dirk


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 Post subject: Re: New minimig build for the DE1
PostPosted: Mon Jan 02, 2012 5:35 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
The code is hosted on github: https://github.com/rkrajnc/minimig-de1

Almost all features from the minimig sources have been implemented, except the already mentioned keyboard mouse & joystick emulation, the new boot code & the "arm replacement" code. I'll work on that first.

In the future, I intent to:
- convert all VHDL code to verilog (I'd like to setup a testbench environment and my simulation tools only work with verilog code)
- write a cache - probably a caching sdram controller, since amiga is a multi-master system
- upgrade the cpu to a 020
- fix most of a large number of timing errors

That's probably all that will comfortably fit into FPGA on a DE1 board, though.

It would also be great if the code in the original minimig repository would be updated to accommodate easier porting to other systems (like avoid using technology and/or vendor specific instances - multipliers, shift-registers, memories, ...) and the toplevel updated to keep all vendor specific stuff outside of it. But I guess that's up to the maintainer (yaqube?).

Incidentally, does anybody know if tobiflexx is intending to release the source to his updated TG68 core? Or the minimig AGA sources?

Enjoy!

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 Post subject: Re: New minimig build for the DE1
PostPosted: Mon Jan 02, 2012 6:54 pm 
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Joined: Thu Jun 18, 2009 9:54 am
Posts: 349
Awesome, chaos! I never though the DE1 was going to get an updated Minimig port!

The DE1 is a great board with inmense potential, too few projects have been released for it considering how versatile and cheap this board is. It's Minimig implementation was the first I ever got to try :)


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 Post subject: Re: New minimig build for the DE1
PostPosted: Tue Jan 03, 2012 11:39 pm 
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Joined: Sun Jan 04, 2009 3:48 am
Posts: 80
chaos wrote:
The code is hosted on github: https://github.com/rkrajnc/minimig-de1

Almost all features from the minimig sources have been implemented, except the already mentioned keyboard mouse & joystick emulation, the new boot code & the "arm replacement" code. I'll work on that first.

In the future, I intent to:
- convert all VHDL code to verilog (I'd like to setup a testbench environment and my simulation tools only work with verilog code)
- write a cache - probably a caching sdram controller, since amiga is a multi-master system
- upgrade the cpu to a 020
- fix most of a large number of timing errors

That's probably all that will comfortably fit into FPGA on a DE1 board, though.

It would also be great if the code in the original minimig repository would be updated to accommodate easier porting to other systems (like avoid using technology and/or vendor specific instances - multipliers, shift-registers, memories, ...) and the toplevel updated to keep all vendor specific stuff outside of it. But I guess that's up to the maintainer (yaqube?).

Incidentally, does anybody know if tobiflexx is intending to release the source to his updated TG68 core? Or the minimig AGA sources?

Enjoy!


Hello,

good luck converting the TG68 VHDL code to Verilog unless you have a professional VHDL to Verilog converter.
The best free tool I found so far is the vhd2vl tool from Ocean Logic : http://www.ocean-logic.com/downloads.htm
It is Lex/Yacc based and can be upgraded easily.

I just finished a 68000 softcore in Verilog called J68. Maybe I should opensource it.
It only takes 1800 LEs and 8 M9k on a Cyclone III (it will be 14 M4k on a Cyclone II).
It runs at 90 MHz but since it is micro-coded, it is like running a real 68000 at 35-40 MHz.
I also tested the core on a Stratix II and got a fmax of 180 MHz 8-)

Regards,

Frederic


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 Post subject: Re: New minimig build for the DE1
PostPosted: Wed Jan 04, 2012 9:42 am 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
frenchshark:

actually, I'm almost done with the tg68 translation. I know about the vhd2vl tool, but last time I tested it, it could only convert simple vhdl constructs. I just did it by hand. There are still some sections I need to check to see whether they are actual flops or just combinatorial logic - sometimes vhdl is hard to read, at least for me :)

Great to hear about your 68k softcore, I hope you'll opensource it :)

Enjoy!

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 Post subject: Re: New minimig build for the DE1
PostPosted: Wed Jan 04, 2012 9:51 am 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
chaos wrote:
sometimes vhdl is hard to read, at least for me :)

Same here, I prefer Verilog :)

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 Post subject: Re: New minimig build for the DE1
PostPosted: Thu Jan 05, 2012 9:37 am 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
boing4000: I see you are also working on minimig rtl code. Now I have to update DE1 build with your changes, too :)

Do you use any kind of open source control (like github, googlecode etc)? It would be really great if minimig versions for different boards could be united in the same repository, since there are now many different implementations (original minimig, DE1 (& DE2), replayboard, ...) and it is a pain-in-the-behind to update each source for every change. DE1 port could easily be included in the original minimig sources with a few #defines and #ifdefs. It would be great if other port's maintainers would hear about this (and possibly agree :)).

Just a thought ;)

Enjoy!

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 Post subject: Re: New minimig build for the DE1
PostPosted: Thu Jan 05, 2012 3:01 pm 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
Until now I only made small updates to the chipset and I don't have upload access to the googlecode area.
Maybe it would be better to upload my sources there too, as you suggested. I will contact Jakub for this.

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 Post subject: Re: New minimig build for the DE1
PostPosted: Sat Jan 14, 2012 12:48 pm 
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Joined: Sat Jan 14, 2012 2:09 am
Posts: 1
Hi,

@chaos: great someone is working on the DE1 port.
I recently purchased a DE1. I tried your build from end of December and it seems to work, although I did not test other builds and can't compare.
Is there a newer build available?

I'am new to this FPGA Stuff, and wanted to lern VHDL, sad that you switch over to Verilog, but good you are further developing the build.

I have seen the data-transfer rate on the DE1 for the SD-Card 390 KByte / second is pretty slow, even my old A500 with Harddisk did approx 500 kByte /second.
On booting the DE1/Minimig says it uses a ARM Core, and looking at the spec of the hardware ARM-Core says there is noMCI-device which could greatly speedup the SD-Card speed. But looking at the DE1 code there seems to be some changings on the ARM code ... Im not sure what is used *puzzled*
But with some help maybe we could speedup the sd-card ...
I have some experience with programming ARM uC and especially Programming SD-Card drivers (with LPC23xx and MCI-device).

Another thing I looked at you github for the sources and see the picture of the Joyport-Adapter ... that one is wrong!
It uses the wrong pins on the PS/2 port. I almost killed my PS/2 Mouse. It got hot because a short fuse (Kurzschluss).
I upload the correct schematic ...


Attachments:
File comment: correct Joyport-adapter Layout
JoysticAdapter_DE1_Minimig_Korrekt.gif
JoysticAdapter_DE1_Minimig_Korrekt.gif [ 40.41 KiB | Viewed 6393 times ]
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