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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Wed Mar 28, 2012 6:31 pm 
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Joined: Tue Dec 13, 2011 7:48 pm
Posts: 341
frenchshark wrote:
The source code is not ready, what's the point in publishing WIP ?

Because someone might look at it and say "Oh, that's a good idea - I can use that trick in my project", or "Oh, I see how you could solve that problem - here, try this."

Open source projects aren't museum pieces. People aren't supposed to look at your beautiful code artifact and gasp in awe - they're supposed to use your code, imperfect as it may be, as a springboard for their own projects, or to try something experimental, and if it works, contribute the result back to you.

For example, because the source code is available, I'm able to experiment with the Chameleon port of the Minimig core. I've already implemented a simple Akiko-style chunky-to-planar converter. The source for my changes is already public even though it's far from perfect. Is it compatible with a "real" Akiko? No. Is it useful? No - it's slower than a CPU-based C2P. Is it interesting? Hell yes - it demonstrates how to add new custom chip registers to the chipset, so someone might find it useful, and that's all that matters!

I'm currently reading, annotating and trying to make sense of the TG68K bridge, so I can have my Akiko running at ZorroII speeds instead of chipram speeds. That work will be released, too, as soon as I have it compiling cleanly and doing something.

Quote:
The 68k is done (somebody on this forum already has it)

That's great :) (Is that the core known as J68?)

Quote:
Agnus is almost done. Then, I have to change Gary and maybe add a cache to the 68k.
Things take time, especially when you want to simulate the whole system.

Indeed - but in many ways a project like this is never "finished" - so release early, and release often :)

_________________
~ Amiga 4000/030 ~ Amiga 1200 030/50MHz ~ Turbo Chameleon 64 ~ Altera DE1 with Minimig core ~
Details of my projects: http://retroramblings.net


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Wed Mar 28, 2012 7:12 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 315
frenchshark: yes I have your J68 sources. Unfortunately, I haven't had the time to look at it much (busy busy :))

Otherwise I agree with gaula92 and MMrobinsonb5 - I know it is not the "Amiga style", but it is the "opensource style" - it is best to release early, as both you and other interested people could benefit from it. You know, the cathedral and the bazaar :)

_________________
** my minimig builds: http://somuch.guru/ **


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Mon Apr 02, 2012 10:01 am 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
I know that this is not much but TG68 core is started somehow. Clock is from external Cristal at 50Mhz. Statement for reset signal :) and core is started. Next stage is to use clk from Amiga board but there are some problems with overheating with ALVT devices, so I need to investigate this.
Code:
sys_rst <= '1';


Image

This is complete code so maybe someone can point me about problems. There are no statements for other signals and don't know do I need to add them for example for as or some other signals. Like I said it is not much but for me it is huge progress. Code is dirty and some of the parts are not used for now but you can get the picture

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity accelerator_top is
   port(
--
-- System level ports
--
-- Port naming convention:
-- Prefix: i = input, o = output, io = inout
-- Sufix: none = active high, n = active low
--
         clk_7             : in std_logic;      --7.09Mhz clock not used for now
         iSYS_CLK            : in std_logic;      -- 50MHz clock
         iSYS_RESETn         : in  std_logic;      -- System Reset
         
         
--
-- ALVT U1 direction         
--
         U1_1DIR_C         : out std_logic;
         U1_1OE_C            : out std_logic;
         U1_2DIR_C         : out std_logic;
         U1_2OE_C            : out std_logic;
--

--
-- ALVT U2 direction         
--
         U2_1DIR_C         : out std_logic;
         U2_1OE_C            : out std_logic;
         U2_2DIR_C         : out std_logic;
         U2_2OE_C            : out std_logic;
--

--
-- ALVT U3 direction         
--
         U3_1DIR_C         : out std_logic;
         U3_1OE_C            : out std_logic;
         U3_2DIR_C         : out std_logic;
         U3_2OE_C            : out std_logic;
--

--
-- ALVT U4 direction         
--
         U4_1DIR_C         : out std_logic;
         U4_1OE_C            : out std_logic;
         U4_2DIR_C         : out std_logic;
         U4_2OE_C            : out std_logic;
--

--
-- LED
--
   LED         : out std_logic;
--         


--
-- TG68 ports
--
        iTG68_IPLn         : in std_logic_vector(2 downto 0):="111";
        iTG68_DTACKn       : in std_logic;
        oTG68_FC            : out std_logic_vector( 2 downto 0);  -- not used on tg68
        oTG68_ADDR           : out std_logic_vector(23 downto 1);
        oTG68_ASn          : out std_logic;
        oTG68_UDSn         : out std_logic;
        oTG68_LDSn         : out std_logic;
        oTG68_RW           : out std_logic;      -- Read = '1', Write = '0'
        ioTG68_DATA          : inout std_logic_vector(15 downto 0);
--
-- MC68K ports that are not supported by the TG68 core
--
         iBERRn            : in    std_logic;
         iVPA               : in     std_logic;
         oVMA               : out   std_logic;
         ioHALT            : inout std_logic;
         iBR               : in    std_logic;
         oBG               : out   std_logic;
         iBGACKn            : in    std_logic;
         oE                  : out   std_logic;
--
-- SDRAM ports
--
         oSDRAM_clk         : out std_logic;
         oSDRAM_cke         : out std_logic;
         oSDRAM_addr         : out std_logic_vector(11 downto 0);
         oSDRAM_cs         : out std_logic;
         oSDRAM_ras         : out std_logic;
         oSDRAM_cas         : out std_logic;
         oSDRAM_we         : out std_logic;
         oSDRAM_io         : out std_logic_vector(4 downto 1);
         oSDRAM_dqm         : out std_logic         
        );
end accelerator_top;

ARCHITECTURE logic OF accelerator_top IS

    COMPONENT TG68
    PORT (
         clk           : in std_logic;
        reset         : in std_logic;
        clkena_in     : in std_logic;
        data_in       : in std_logic_vector(15 downto 0);
        IPL           : in std_logic_vector(2 downto 0);
        dtack         : in std_logic;
        addr          : out std_logic_vector(31 downto 0);
        data_out      : out std_logic_vector(15 downto 0);
        as            : out std_logic;
        uds           : out std_logic;
        lds           : out std_logic;
        rw            : out std_logic
        );
    END COMPONENT;

-- pll not used for now
--   COMPONENT pll
--   PORT (
--      areset      : IN STD_LOGIC;
--      inclk0      : IN STD_LOGIC;
--      c0            : OUT STD_LOGIC;
--      locked      : OUT STD_LOGIC
--   );
--   END COMPONENT;


--
-- TG68 signals
--   
signal data_out          : STD_LOGIC_VECTOR (15 downto 0);
signal dtack_not         : std_logic;
signal tg68_reset       : std_logic;
signal as               : std_logic;
signal rw               : std_logic;
signal uds               : std_logic;
signal lds               : std_logic;
--
-- PLL signals
--
signal sys_rst            : std_logic;
signal sys_clk            : std_logic;
signal clk_14MHz         : std_logic; -- not used
--
-- Reset signals
--
signal reset1            : std_logic;
--
--
signal data_oe     : std_logic;

BEGIN


-- not used for now there is some error that I dont understand
    -- Register input reset signal
-- reset_sync: process(sys_clk)
--    begin
--      if iSYS_CLK'event and iSYS_CLK = '1' then
--         reset1   <= iSYS_RESETn;   -- Sync through 2 registers
--         sys_rst  <= not reset1;      -- Synchronized active high reset
--      end if;
--   end process;


-- dtack_not <= iTG68_DTACKn;   -- Invert DTACK: active low on a real MC68K, but the TG68 core is active high MAYBE ???



-- pll_inst: pll
--   PORT MAP (
--      areset      => sys_rst,
--      inclk0      => iSYS_CLK,         -- 50MHz system clock
--      c0            => clk_14MHz,         -- TG68 clock
--      locked      => open
--   );


TG68_inst: TG68
    PORT MAP (
        data_in           => ioTG68_DATA,      -- change on later versions once ths SDRAM controller or other blocks are added
        data_out          => data_out,
        clk               => iSYS_CLK, -- 50Mhz clk
        reset             => sys_rst,
        clkena_in         => '1',
        IPL               => iTG68_IPLn,
        dtack             => iTG68_DTACKn,
        addr(31 downto 24) => open,
        addr(23 downto 1) => oTG68_ADDR,
        addr(0)           => open,
        as                => as,
        rw                => rw,
        uds               => uds,
        lds               => lds
        );
       

   data_oe <= (not as) and (not rw) and (not uds);

   -- Tri-state bus
   ioTG68_DATA <= (others => 'Z') when (data_oe = '0') else data_out;
--
-- Assign ports
--
   oTG68_ASn   <= as;
   oTG68_RW      <= rw;
   oTG68_UDSn   <= uds;
   oTG68_LDSn   <= lds;
--
-- Stub out unused ports until the code is added to this project
--
      
   oVMA         <= '1';
   ioHALT      <= 'Z';
   oBG         <= '1';
   oE            <= '1';
   oSDRAM_clk   <= '1';
   oSDRAM_cke   <= '1';
   oSDRAM_addr   <= "111111111111";
   oSDRAM_cs   <= '1';
   oSDRAM_ras   <= '1';
   oSDRAM_cas   <= '1';
   oSDRAM_we   <= '1';
   oSDRAM_io   <= "1111";
   oSDRAM_dqm   <= '1';

--
-- ALVT U1 direction         
--

         U1_1DIR_C         <= '0';
         U1_1OE_C            <= '0';
         U1_2DIR_C         <= '0';
         U1_2OE_C            <= '0';
--

--
-- ALVT U2 direction change regarding to data flow maybe not best solution         
--

         U2_1DIR_C         <= not data_oe;
         U2_1OE_C            <= '0';
         U2_2DIR_C         <= not data_oe;
         U2_2OE_C            <= '0';
--

--
-- ALVT U3 direction         
--

         U3_1DIR_C         <= '1';
         U3_1OE_C            <= '0';
         U3_2DIR_C         <= '1';
         U3_2OE_C            <= '0';
--

--
-- ALVT U4 direction         
--

         U4_1DIR_C         <= '1';
         U4_1OE_C            <= '0';
         U4_2DIR_C         <= '1';
         U4_2OE_C            <= '0';
--

--
-- LED
--

      LED <= not data_oe;
--         


      sys_rst <= '1';
      
END;   


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Mon Apr 02, 2012 4:21 pm 
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Joined: Mon Dec 07, 2009 3:53 pm
Posts: 26
@FrenchShark,
So you did most of the MCC216 ?
I'm 'happy' owner of one. I use the C64(your flagship product) mostly but the ps2key 'right shift problem' always gets to me. I've to re-type what I've typed just to get out of that situation.
when typing in basic (when R-shift is pressed too fast with another key). It's a known problem. All my PS2 keyboards (x3) have this problem including the Microsoft keyboard. I'm not buying the Genius KB120 as recommended by some people. Pls have a look see on this. TKU

L@K


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Apr 08, 2012 8:48 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
So it should be something like that

process (clk_7Mhz, TG68_reset)
begin
if TG68_reset = '0' then
-- WHAT THEN

elsif rising_edge(clk_7Mhz) then
-- WHAT THEN
end if;
end process;


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Wed Oct 10, 2012 8:15 am 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
In 3 wire bus arbitration on MC68K key signals are BR, BG, BGACK but those signals have some dependency of signals present on real MC68K so if we need to use them to start arbitration with FPGA some signals needs to be threaded like input and output one in the same time.

3 wire bus arbitration works this way.
FPGA sends BR(active low) to real CPU and he confirms that by sending BG(active low) to FPGA, then FPGA waits for MC68K to finish current cycle and then sends BGACK to MC68K to confirm that FPGA now have control of the bus. After that FPGA negates BR and MC68K confirms that by negating BG and waiting for BGACK to be negated. In that time FPGA performs read and write cycles and after finishing negates BGACK and next arbitration begins.
So in this case to send BR we need to separate it into inputBR and outputBR signal, also need to be done with AS, BGACK and some more signals.
Also direction control of ALVC devices needs to change direction in cases when we need to read or write signal.

So in the process inputBR is checked and if he is negated inputoutputBR connected to outputBR signal who goes low sending Bus Request. After that ioBGACKn is over obgack_s checking signals on real CPU to find out that he finished his bus cycle and then he sends active low signal to the real CPU, the same time ALVC devices changes their direction, so new states could be sent to real CPU.


ias_s <= ioTG68_ASn when U3_1DIR_C = '0' else 'Z';
ibr_s <= ioBR;
ibgack_s <= ioBGACKn;

obr_s <= '0';
obgack_s <= 'Z' when (iBG = '1' and ias_s ='1' and dtack_s ='1' and ibgack_s = '1') else '0' when (iBG = '0' and ias_s = '1' and dtack_s ='1');

process (ibr_s)
begin
if ibr_s = '1' and U3_1DIR_C = '0' then
ioBR <= obr_s;
ioBGACKn <= obgack_s;
U3_1DIR_C <= '1';
U3_1OE_C <= '0';
elsif ibr_s = '0' and obgack_s = '0' then
ioBR <= '1';
end if;
end process;

So all of this should be separated into different processes and it could be done for day or two but only question I may ask here is all of this necessary, is there any simpler way to disable CPU or he must stay active in some bus cycles. Thank you


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Jan 13, 2013 1:27 am 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
After so much questions here some results. TG68 code integrated and I must say that all of previous codes that I have published here was unusable. I just had to find another way to integrate all of this. Most important thing for now that I was trying to run core at 14 Mhz but without any luck because it could be hard to keep original 7.09Mhz bus cycles and in the same time increase performance.
http://youtu.be/JkkKMrUkJtE


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