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 Post subject: Tg68 in altera Cyclone II questions
PostPosted: Fri Jan 28, 2011 1:20 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
I m sorry to ask something again, and probably answer is allready on the forum. But i cant find it, i have hard time translating to english, and searching in german.

I want to use TG68 core, and i execute it in Altera Quartus and all works fine.
My questions are.
1. What are differences between Cyclone II and Cyclone III And Spartan III related to speed and compatibility?
2. I want to use this board based on EP2C5T144 Altera Cyclone II
Can i do something using this board http://cgi.ebay.de/EP2C5T144-Altera-CycloneII-FPGA-mini-Development-Board-/280608972510?pt=BI_Electrical_Equipment_Tools&hash=item4155991ede

3. Can i use some other boards based on some other FPGA.

4. Can it be done to connect SDRAM controller to TG68.


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Fri Jan 28, 2011 11:38 pm 
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Joined: Sun Jan 04, 2009 3:48 am
Posts: 80
majsta wrote:
1. What are differences between Cyclone II and Cyclone III And Spartan III related to speed and compatibility?

The speed is about the same. I know quite well the Cyclone serie, between the generation speed gets slightly better and power consumption (and price) decreases.

majsta wrote:
2. I want to use this board based on EP2C5T144 Altera Cyclone II
Can i do something using this board http://cgi.ebay.de/EP2C5T144-Altera-CycloneII-FPGA-mini-Development-Board-/280608972510?pt=BI_Electrical_Equipment_Tools&hash=item4155991ede

Not enough LEs, I would recommend at least 10KLEs, 16KLEs is better and 25KLEs is perfect.

majsta wrote:
3. Can i use some other boards based on some other FPGA.

Look at the terasic ones : DE0, DE1 or DE2 or I you prefer Xilinx, the latest ATLYS board from digilent looks awesome.

majsta wrote:
4. Can it be done to connect SDRAM controller to TG68.

I have a design running with an SDRAM controller, a TG68 (soon to be replaced by an AO68000) and the Minimig core.
It takes ~13KLEs.

Regards,

Frederic


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sat Jan 29, 2011 3:04 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
Ok thanks, i have some more questions.
1. In order to use Cyclone board to replace MC68000 processor i need to solve 5V I/O ports problem. Do you have some ideas.
2: TG68K core and SDRAM controller. If i connect controller do i get better performance because when i worked with some other CPU-s i only get acceleration with i use additional memory, without memory there is no significant acceleration. What is the situation regarding to this with FPGA.


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sat Feb 05, 2011 3:14 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
Ok i solved 5V problem with quickswichs, but now i have problems with pin planner. There is more pins that are in standard 68 pin mc68000. Ok i understand most things, but what i can do with Data_in and Data_write. Is this Data Bus D0-D15 I/O on MC68k because if it is i dont know how to assign those pins, because i have 16 Data_in and the same number od Data_write, i cant combine them to get 16 Data Bus pins and then to connect it to Mc68k. I need to use 32 pins and what to do with them i cant connect it to 16 pins of Data Bus.


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sat Feb 05, 2011 4:32 pm 
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Joined: Mon Dec 01, 2008 10:11 am
Posts: 197
majsta wrote:
Ok i understand most things, but what i can do with Data_in and Data_write. Is this Data Bus D0-D15 I/O on MC68k because if it is i dont know how to assign those pins, because i have 16 Data_in and the same number od Data_write, i cant combine them to get 16 Data Bus pins and then to connect it to Mc68k. I need to use 32 pins and what to do with them i cant connect it to 16 pins of Data Bus.

You should directly connect the data_in signals to the CPU data bus. The data_out signals must be connected to the same CPU data pins through tri-state buffers (located in the I/O cells in the FPGA). The buffers should be enabled whenever AS and R/W signals are both low.


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Feb 06, 2011 4:48 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
Thank you but... No, there is no way that i can understand this. All day i m searching but nothing. I m trying in Block Diagram with Pimitives/Buffer/tri. I m trying in Assignment editor and auto open drain pins and no way. Then i checked .qsf file and add set_global_assignment -name TRI_STATE_SPI_PINS ON . I was reading all day, in all forums but i just dont understand.


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Feb 06, 2011 7:22 pm 
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Joined: Mon Dec 01, 2008 10:11 am
Posts: 197
majsta wrote:
Thank you but... No, there is no way that i can understand this. All day i m searching but nothing. I m trying in Block Diagram with Pimitives/Buffer/tri. I m trying in Assignment editor and auto open drain pins and no way. Then i checked .qsf file and add set_global_assignment -name TRI_STATE_SPI_PINS ON . I was reading all day, in all forums but i just dont understand.

Just put at the top level the following statement:

data <= data_out WHEN as='0' AND rw='0' ELSE (OTHERS => 'Z');
data_in <= data;


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Feb 06, 2011 9:19 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
No way, i m trying for last 2 hours. I must be f*****g stupid. It cant be so complicated i dont understand where I'm going wrong. I inserted your code in TG68.vhd and all i get is number of errors. Then again i was trying to use schematics and again no luck. I m working with computers more then 20 years but i cant see where i m going wrong. As i can say again. It is most like that i m stupid.

Image


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Feb 06, 2011 9:37 pm 
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Joined: Sun Jan 04, 2009 3:48 am
Posts: 80
Bidirectional pins is a common difficulty in HDL.
Just Google for VHDL or Verilog examples with the words "tristate", "inout" or "bidir".
Inside an FPGA (and I guess any VLSI chip), there is no bidirectional signals so the data busses are splitted into two busses.
They become one bus again when they exit the chip thanks to the use of a bidirectional buffer (a tristate buffer + an input buffer).

Here is a short example in VHDL:

The port declaration:
data_bus : inout STD_LOGIC_VECTOR(15 downto 0)

The signals declarations:
signal s_data_out : STD_LOGIC_VECTOR(15 downto 0);
signal s_data_in : STD_LOGIC_VECTOR(15 downto 0);
signal s_data_oe : STD_LOGIC;

The combinatorial logic:
data_bus <= s_data_out when (s_data_oe = '1') else (others=> 'Z');
s_data_in <= data_bus;

You can see that even when you output something on the pins, you can still read back the pins at the same time.

Do not use schematics entry, just use a VHDL or Verilog wrapper that will be your design top-level.

Hope it helps

Frederic


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Mon Feb 07, 2011 11:58 am 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
Ok i created new VHDL called Vhd1.vhd file and in that file i import this.
--------------
data <= data_out WHEN as='0' AND rw='0' ELSE (OTHERS => 'Z');
data_in <= data;
--------------
Then i use Set as Top-Level Entity for that file, then i go to compile and i get this error
----------------------
Error (10500): VHDL syntax error at Vhdl1.vhd(1) near text "data"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
----------------------
I understand this error but you did not tell me to add any of them.


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