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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Mon Feb 07, 2011 8:52 pm 
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Joined: Sun Jan 04, 2009 3:48 am
Posts: 80
majsta wrote:
Ok i created new VHDL called Vhd1.vhd file and in that file i import this.
--------------
data <= data_out WHEN as='0' AND rw='0' ELSE (OTHERS => 'Z');
data_in <= data;
--------------
Then i use Set as Top-Level Entity for that file, then i go to compile and i get this error
----------------------
Error (10500): VHDL syntax error at Vhdl1.vhd(1) near text "data"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
----------------------
I understand this error but you did not tell me to add any of them.


This was just a code snippet that needs to be added to your top level entity.
You have to create an entity and an architecture with all the I/Os declarations, components declarations, then you instantiate your components and you wire them up to your I/Os.
Please have a look at some VHDL or Verilog manuals.
VHDL is like ADA language, Verilog is closer to C language. They are both well suited for what you want to do. Verilog is easier to learn.

Regards,

Frederic


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Tue Feb 08, 2011 1:05 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
Thank you. I was reading, searching and managed to make some code. But it does not work. Also i was trying usinf IF command insted WHEN and i did not make it work. I understand what is happening in code but i think that i did not add some part. VHDL code i was working on all morning.
Update1: Code is working now but i dont see ADRESS BUSS lines in pin planner, and also there is data_bus as bidir group, and also input and output group all with 16 pins? As i can see my code have influence on all pins, and i just want to have influence on 16 in and 16 out pins.
Only generated 49 pins, before it was 70.
Update2: I dont understand why i need to declare all signals etc... All components are allready in TG.vhd. I only need to add inout part. I think that i need to connect TG68.vhd to this code and then reuse all declared in TG68.vhd.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY data_bus IS
PORT(
data_bus : inout STD_LOGIC_VECTOR (15 downto 0);
oe : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END data_bus;

ARCHITECTURE signals OF data_bus IS
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);
signal data_oe : STD_LOGIC;

BEGIN
PROCESS(oe)
BEGIN
IF oe = '1' THEN
data_bus <= data_out;
ELSE
data_bus <= "ZZZZZZZZZZZZZZZZ";
data_in <= data_bus;

END IF;
END PROCESS;
END signals;



Last edited by majsta on Tue Feb 08, 2011 10:01 pm, edited 1 time in total.

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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Tue Feb 08, 2011 9:42 pm 
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Joined: Sun Jan 04, 2009 3:48 am
Posts: 80
majsta wrote:
Thank you. I was reading, searching and managed to make some code. But it does not work. Also i was trying usinf IF command insted WHEN and i did not make it work. I understand what is happening in code but i think that i did not add some part. VHDL code i was working on all morning.
Update: Code is working now but i dont see ADRESS BUSS lines in pin planner, and also there is data_bus as bidir group, and also input and output group all with 16 pins? As i can see my code have influence on all pins, and i just want to have influence on 16 in and 16 out pins.
Only generated 49 pins, before it was 70.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY data_bus IS
PORT(
data_bus : inout STD_LOGIC_VECTOR (15 downto 0);
oe : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END data_bus;

ARCHITECTURE signals OF data_bus IS
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);
signal data_oe : STD_LOGIC;

BEGIN
PROCESS(oe)
BEGIN
IF oe = '1' THEN
data_bus <= data_out;
ELSE
data_bus <= "ZZZZZZZZZZZZZZZZ";
data_in <= data_bus;

END IF;
END PROCESS;
END signals;



That's a good start. Now, you have to add the component declaration of the TG68 and instantiate it.
Create some signals and wire the TG68 to the ports of your top level.

The IF can only be used in a PROCESS. The WHEN can be used outside a PROCESS.
The same apply with the CASE (in a PROCESS) and the SELECT (outside).

In 99.9% of the case, what is ouside a PROCESS is combinatorial.

Regards,

Frederic


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Tue Feb 08, 2011 10:07 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
I generated components from tg68 and then inserted in my top level design but i m stuck again. Can you explane me better what i need to do.


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun May 08, 2011 8:55 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
I did not solve the problem. Is there anyone who can help ?


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sat Jul 02, 2011 8:56 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
I solved this one but i have another problem regarding adding sdram controller to tg68 core. I was looking some designs but without real examples. Can anyone point me where to go from here.


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Mar 11, 2012 12:33 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
Again need help. With some help I created top level design file for TG68 and done some simulations but when I program core to FPGA I can't detect any signal movements. Hardware is ok because when I use any other simple designs for testing CLK and LEDs with signaltap I can see all the signals. Just like TG68 is not started or does not have clock I provided ?

Here is code and notice there are some voltage level translators on design but those are not important here, Tg68 just won't start. Do I need to provide some additional instructions here to start it or something. Also there is part of SDRAM controller that s not integrated, just point your attention to tg68 signals

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity accelerator_top is
   port(
--
-- System level ports
--
-- Port naming convention:
-- Prefix: i = input, o = output, io = inout
-- Sufix: none = active high, n = active low
--
         clk_7             : in std_logic;      --7.09Mhz clock just for testing, not used in design
         iSYS_CLK            : in std_logic;      -- 50MHz clock
         iSYS_RESETn         : in  std_logic;      -- System Reset
         
         
--
-- ALVT U1 direction         
--
         U1_1DIR_C         : out std_logic;
         U1_1OE_C            : out std_logic;
         U1_2DIR_C         : out std_logic;
         U1_2OE_C            : out std_logic;
--

--
-- ALVT U2 direction         
--
         U2_1DIR_C         : out std_logic;
         U2_1OE_C            : out std_logic;
         U2_2DIR_C         : out std_logic;
         U2_2OE_C            : out std_logic;
--

--
-- ALVT U3 direction         
--
         U3_1DIR_C         : out std_logic;
         U3_1OE_C            : out std_logic;
         U3_2DIR_C         : out std_logic;
         U3_2OE_C            : out std_logic;
--

--
-- ALVT U4 direction         
--
         U4_1DIR_C         : out std_logic;
         U4_1OE_C            : out std_logic;
         U4_2DIR_C         : out std_logic;
         U4_2OE_C            : out std_logic;
--

--
-- LED
--
   LED         : out std_logic;
--         


--
-- TG68 ports
--
        iTG68_IPLn         : in std_logic_vector(2 downto 0):="111";
        iTG68_DTACKn       : in std_logic;
        oTG68_FC            : out std_logic_vector( 2 downto 0);  -- not used on tg68
        oTG68_ADDR           : out std_logic_vector(23 downto 1);
        oTG68_ASn          : out std_logic;
        oTG68_UDSn         : out std_logic;
        oTG68_LDSn         : out std_logic;
        oTG68_RW           : out std_logic;      -- Read = '1', Write = '0'
        ioTG68_DATA          : inout std_logic_vector(15 downto 0);
--
-- MC68K ports that are not supported by the TG68 core
--
         iBERRn            : in    std_logic;
         iVPA               : in     std_logic;
         oVMA               : out   std_logic;
         ioHALT            : inout std_logic;
         iBR               : in    std_logic;
         oBG               : out   std_logic;
         iBGACKn            : in    std_logic;
         oE                  : out   std_logic;
--
-- SDRAM ports
--
         oSDRAM_clk         : out std_logic;
         oSDRAM_cke         : out std_logic;
         oSDRAM_addr         : out std_logic_vector(11 downto 0);
         oSDRAM_cs         : out std_logic;
         oSDRAM_ras         : out std_logic;
         oSDRAM_cas         : out std_logic;
         oSDRAM_we         : out std_logic;
         oSDRAM_io         : out std_logic_vector(4 downto 1);
         oSDRAM_dqm         : out std_logic         
        );
end accelerator_top;

ARCHITECTURE logic OF accelerator_top IS

    COMPONENT TG68
    PORT (
         clk           : in std_logic;
        reset         : in std_logic;
        clkena_in     : in std_logic;
        data_in       : in std_logic_vector(15 downto 0);
        IPL           : in std_logic_vector(2 downto 0);
        dtack         : in std_logic;
        addr          : out std_logic_vector(31 downto 0);
        data_out      : out std_logic_vector(15 downto 0);
        as            : out std_logic;
        uds           : out std_logic;
        lds           : out std_logic;
        rw            : out std_logic
        );
    END COMPONENT;


   COMPONENT pll
   PORT (
      areset      : IN STD_LOGIC;
      inclk0      : IN STD_LOGIC;
      c0            : OUT STD_LOGIC;
      locked      : OUT STD_LOGIC
   );
   END COMPONENT;


--
-- TG68 signals
--   
signal data_out          : STD_LOGIC_VECTOR (15 downto 0);
signal dtack_not         : std_logic;
signal tg68_reset       : std_logic;
signal as               : std_logic;
signal rw               : std_logic;
signal uds               : std_logic;
signal lds               : std_logic;
--
-- PLL signals
--
signal sys_rst            : std_logic;
signal sys_clk            : std_logic;
signal clk_14MHz         : std_logic;
--
-- Reset signals
--
signal reset1            : std_logic;
--
--
signal data_oe     : std_logic;

BEGIN



    -- Register input reset signal
reset_sync: process(sys_clk)
    begin
      if iSYS_CLK'event and iSYS_CLK = '1' then
         reset1   <= iSYS_RESETn;   -- Sync through 2 registers
         sys_rst  <= not reset1;      -- Synchronized active high reset
      end if;
   end process;


dtack_not <= NOT iTG68_DTACKn;   -- Invert DTACK: active low on a real MC68K, but the TG68 core is active high



pll_inst: pll
   PORT MAP (
      areset      => sys_rst,
      inclk0      => iSYS_CLK,         -- 50MHz system clock
      c0            => clk_14MHz,         -- TG68 clock
      locked      => open
   );


TG68_inst: TG68
    PORT MAP (
        data_in           => ioTG68_DATA,      -- change on later versions once ths SDRAM controller or other blocks are added
        data_out          => data_out,
        clk               => clk_14MHz,
        reset             => sys_rst,
        clkena_in         => '1',
        IPL               => iTG68_IPLn,
        dtack             => dtack_not,
        addr(31 downto 24) => open,
        addr(23 downto 1) => oTG68_ADDR,
        addr(0)           => open,
        as                => as,
        rw                => rw,
        uds               => uds,
        lds               => lds
        );
       

   data_oe <= (not as) and (not rw) and (not uds);

   -- Tri-state bus
   ioTG68_DATA <= (others => 'Z') when (data_oe = '0') else data_out;
--
-- Assign ports
--
   oTG68_ASn   <= as;
   oTG68_RW      <= rw;
   oTG68_UDSn   <= uds;
   oTG68_LDSn   <= lds;
--
-- Stub out unused ports until the code is added to this project
--
      
   oVMA         <= '1';
   ioHALT      <= 'Z';
   oBG         <= '1';
   oE            <= '1';
   oSDRAM_clk   <= '1';
   oSDRAM_cke   <= '1';
   oSDRAM_addr   <= "111111111111";
   oSDRAM_cs   <= '1';
   oSDRAM_ras   <= '1';
   oSDRAM_cas   <= '1';
   oSDRAM_we   <= '1';
   oSDRAM_io   <= "1111";
   oSDRAM_dqm   <= '1';

--
-- ALVT U1 direction         
--

         U1_1DIR_C         <= '0';
         U1_1OE_C            <= '0';
         U1_2DIR_C         <= '0';
         U1_2OE_C            <= '0';
--

--
-- ALVT U2 direction         
--

         U2_1DIR_C         <= not data_oe;
         U2_1OE_C            <= '0';
         U2_2DIR_C         <= not data_oe;
         U2_2OE_C            <= '0';
--

--
-- ALVT U3 direction         
--

         U3_1DIR_C         <= '1';
         U3_1OE_C            <= '0';
         U3_2DIR_C         <= '1';
         U3_2OE_C            <= '0';
--

--
-- ALVT U4 direction         
--

         U4_1DIR_C         <= '1';
         U4_1OE_C            <= '0';
         U4_2DIR_C         <= '1';
         U4_2OE_C            <= '0';
--

--
-- LED
--

      LED <= not data_oe;
--         


      
      
END;   


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Mar 11, 2012 2:40 pm 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
2 things:
- What condition is RESET signal?
- ioHALT is defined to "Z" which means tristate-high level. Im not sure if this signal is actice Hi or Lo in TG68k.

(VHDL will never do it for me...)

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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Mar 11, 2012 2:48 pm 
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Joined: Sun Jan 23, 2011 9:36 pm
Posts: 21
Regarding ioHALT HALT is not implemented to TG68 as I know. TG68 is either not working on standalone version with tg68.vhd used for top level design file and provided basic clk directly without pll. When i try to program that to FPGA there are no signals detected with signaltap?


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 Post subject: Re: Tg68 in altera Cyclone II questions
PostPosted: Sun Mar 11, 2012 8:55 pm 
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Joined: Sun Jan 04, 2009 3:48 am
Posts: 80
Hello,

I think you should try to have the TG68 running from a small RAM/ROM implemented within the FPGA.
Start with the minimal ROM : the reset vectors and an endless loop. Verify that the TG68 runs as expected with signaltap.
Then, add more instruction and create an "Hello world" program in ASM.
The best would be to have some test pins on the FPGA board that you can use for a UART implementation.
Then, you can debug with this kind of cable : http://www.ftdichip.com/Products/Cables ... Serial.htm
Once you have that running, you can start accessing the external world : the A600 bus.

Regards,

Frederic


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