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 Post subject: Re: Copper issue
PostPosted: Thu May 08, 2014 5:37 pm 
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madeho wrote:
1) Issue w/ WAIT instruction for horizontal position $E2.


Both real Amiga(500 OCS) and Minimig show no copper bars with a WAIT at $xxE2
At $xxE1 and $xxE3 all is fine.

This simply is because:
$xxE2,$FFFE is decoded by Copper as: MOVE #$FFFE,$xE2 ("bpl0ptl" or "hcenter ECS" register).
WAIT always need an odd horizontal address to be decoded.

Right now I realize Amiga Chipset is a true masterpice by design :)

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 Post subject: Re: Copper issue
PostPosted: Thu May 08, 2014 7:38 pm 
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Hi boing,

boing4000 wrote:
Both real Amiga(500 OCS) and Minimig show no copper bars with a WAIT at $xxE2

By 'WAIT instruction for horizontal position $E2' I mean that in a copper list it will be $00E3, $80FE (as it was in a bootrom)
boing4000 wrote:
At $xxE1 and $xxE3 all is fine.

Both Amiga and Minimig shall generates the same bars pattern for a value $00E1 (many bars in a blue, gren and red colour, 16 lines high). Do they do the same for a value $00E3? I couldn't get bars pattern w/ a latest core (FBS140414_r2) for a value $00E3. On minimig, screen was green to a line 127 and red below it.


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 Post subject: Re: Copper issue
PostPosted: Mon May 12, 2014 9:28 pm 
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chaos wrote:
I wouldn't blindly trust the simulation results, unless you thoroughly checked the code also.

Hi chaos,

I think I can trust my simulation setup. I needed only 2 builds to get reimplemented copper working great, all work was done w/ a use of functional simulation. After 1st build it was working good w/ up to 4 bitplanes (I forgot to extend timing for a non-dma cycles of WAIT and SKIP instructions). Even these Dexion Megademo worked fine. On a 2nd build timing was improved (thx to a simulation) and the result was perfect. That time also Copper Master demo by Angels works great too (it uses 5 or 6 bitplanes)
Reimplementation also fixes some issues found in a verilog implementation:
- WAIT/SKIP for a last position in a line doesn't finish on it,
- it is possible to make MOVE instruction even to a read only registers in ECS mode ,
- copper is not restarted on a COPJMP write after illegal address stop. it restarts only on SOF event

Attached are modified/new files needed to build a bin file


Attachments:
vhdl_copper.zip [24.14 KiB]
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 Post subject: Re: Copper issue
PostPosted: Tue May 13, 2014 2:01 pm 
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Posts: 315
Hi madeho,

I believe you, I just wanted to inform you of some potential pitfalls with simulating minimig code that I had to deal with already.

I'll try to check your changes as soon as I can.

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 Post subject: Re: Copper issue
PostPosted: Sat May 17, 2014 6:51 pm 
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Hi madeho,

I tried both the Megademo and Copper Master demos with the current minimig-de1 code, and I don't think I saw any problems (I ran it simultaneously with WinUAE, unfortunately I don't have a real Amiga here right now). Can you please describe which part of the demo has problems currently, or maybe even add a screenshot, so I'll know what to look for. Thanks!

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 Post subject: Re: Copper issue
PostPosted: Mon May 19, 2014 4:23 pm 
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Hi chaos,
chaos wrote:
I tried both the Megademo and Copper Master demos ... and I don't think I saw any problems

There is no problems w/ these demos, I use them as a good reference points to test Copper compatibility. Even w/ a small extension from an original design they will be corrupted in some parts.
The real issue (I'm almost 100% confident) is that an official minimig's copper implementation (verilog one), is not able to wait for beam counter equal to $E2. According to HRM it shall be possible and there is an example which wait until position $E2 will be reached. That WAIT instruction ($00E3, $80FE) was used to wait for the end of specific line.
During a tests on minmimig (modified bootrom code attached earlier on that topic) doesn't break wait condition when $E2 position is reached by beam counter. It waits infinitely until SOF condition appear and copper program counter will be restarted.


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 Post subject: Re: Copper issue
PostPosted: Mon May 19, 2014 7:14 pm 
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Location: .de
Do you have an ADF with the ASM source?
This would be a big help to check and compare against real Amiga chipset hardware.

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 Post subject: Re: Copper issue
PostPosted: Thu May 22, 2014 9:24 pm 
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boing4000 wrote:
Do you have an ADF with the ASM source?

Attached ADF image w/ asmone and test.s source to run on a real HW


Attachments:
work.adf [880 KiB]
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 Post subject: Re: Copper issue
PostPosted: Sat May 24, 2014 5:21 pm 
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Location: .de
madeho wrote:
Attached ADF image w/ asmone and test.s source to run on a real HW


Now, this program Copperlist looks 100% the same on Minimig and real OCS Amiga500.
I see an splitted upper green and lower red screen.

On Minimig the result is the same at any chipset setting.
The real Amiga500 has an 8371 FatAgnus and an OCS Denise chip.
Later: Also tested on ECS Amiga500+ with the same result.

By now, there is no problem present.
Or maybe some IRQ in the test program is not set right? I've never played much with those things ;)

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 Post subject: Re: Copper issue
PostPosted: Wed May 28, 2014 5:31 pm 
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Hi boing,

Thx for testing.
boing4000 wrote:
Now, this program Copperlist looks 100% the same on Minimig and real OCS Amiga500.
I see an splitted upper green and lower red screen.

It seams that there is a big discrepancy between real HW and description provided in Amiga HRM. This Copper list was used to illustrate how SKIP instruction works. According to a copper list comments, it shall trigger Copper interrupt every 16 lines.
In real it doesn't work like that ....


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