I wouldn't blindly trust the simulation results, unless you thoroughly checked the code also.
I think I can trust my simulation setup. I needed only 2 builds to get reimplemented copper working great, all work was done w/ a use of functional simulation. After 1st build it was working good w/ up to 4 bitplanes (I forgot to extend timing for a non-dma cycles of WAIT and SKIP instructions). Even these Dexion Megademo worked fine. On a 2nd build timing was improved (thx to a simulation) and the result was perfect. That time also Copper Master demo by Angels works great too (it uses 5 or 6 bitplanes)
Reimplementation also fixes some issues found in a verilog implementation:
- WAIT/SKIP for a last position in a line doesn't finish on it,
- it is possible to make MOVE instruction even to a read only registers in ECS mode ,
- copper is not restarted on a COPJMP write after illegal address stop. it restarts only on SOF event
Attached are modified/new files needed to build a bin file