Hi madeho, nice work.
Minimig is not completely cycle-exact to real hardware, so I wouldn't worry about that, unless there's a bug in some software.
Thx, I know that it isn't cycle-exact
in a real Amiga one HPOS increments on each CCK but it also only updates bits from 8 to 1. Minimig uses 7MHz clock to increment that counter and bit 0 shall be used as a kind of prescaler. That why theoreticaly it shall count in a 'normal' way (0, 1, 2, 3, .....)
Regarding the hpos counter, it does look like something might be wrong there, as bit 0, which is a non-registered version of cck signal, toggles at the wrong time (or the +2 counter is incremented at the wrong time), that's why it's counting in that order.
Thx again, from a code I can read why it count in that strange way .... my question was more: "Is it intended to be like that or maybe it is a bug which was introduced during migration to a 7MHz clock domain?"
How are you simulating this - are you using proper CPU / chipset timings, as that would be my first guess as to what is wrong?
This is not timing simulation it is only behavioral one. I use a real Minimig modules to get a proper set of signals needed to my development. I've found this out because I needed to simulate DMA engine and I decided to use Agnus to generate all of them.