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 Post subject: Beam counter issue?
PostPosted: Thu Mar 28, 2013 1:24 pm 
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Joined: Fri Jan 20, 2012 9:32 pm
Posts: 55
During some tests I have found strange behavior of a beem counter (look at an attached screenshot). It counts in a really strange way, which is correct from an implementation point of view but it shouldn't work like this I guess.
For me, it can cause some mismatch in DMA slots allocation. Each DMA engine uses all bits or some of LSB bits of a HPOS couter to detect slot assigned to it eg.
Code:
// bitplane dma enable bit delayed by 4 CCKs
always @(posedge clk)
   if (hpos[1:0]==2'b11)
      dmaena_delayed[1:0] <= {dmaena_delayed[0], dmaena};

VPOS counter is also updated 1 clk tick to earlier than it should be .... additionally when it is reset by VHPOSW write it doesn't 'reach' value 1, it counts 0,3,2 .... on 2 VPOS counter is incremented.
Code:
//vertical counter increase
always @(posedge clk)
   if (hpos==2) //actual chipset works in this way
      vpos_inc <= 1'b1;
   else
      vpos_inc <= 1'b0;

//vertical position counter
//vpos changes after hpos equals 3
always @(posedge clk)
   if (reg_address_in[8:1]==VPOSW[8:1])
      vpos[10:8] <= data_in[2:0];
   else if (reg_address_in[8:1]==VHPOSW[8:1])
      vpos[7:0] <= data_in[15:8];
   else if (vpos_inc)
      if (last_line)
         vpos <= 0;
      else
         vpos <= vpos + 1;


I don't know all of details of a design ... maybe it is intended behavior, but for me it looks like some kind of a bug in it. Can anyone else look at this?


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beam_counter_issue.jpg
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 Post subject: Re: Beam counter issue?
PostPosted: Thu Mar 28, 2013 2:31 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
Hi madeho, nice work.

Minimig is not completely cycle-exact to real hardware, so I wouldn't worry about that, unless there's a bug in some software.

Regarding the hpos counter, it does look like something might be wrong there, as bit 0, which is a non-registered version of cck signal, toggles at the wrong time (or the +2 counter is incremented at the wrong time), that's why it's counting in that order. Definitely worth taking a better look.

How are you simulating this - are you using proper CPU / chipset timings, as that would be my first guess as to what is wrong?

EDIT: after another inspection of your waveforms, it seems something is wrong with your simulation. First of all, clk28m and clk7m should be edge-aligned, synchronous clocks, which doesn't seem to be the case in your simulation. And if you look at the transition of hpos from 0 to 3, you can see that that transition shouldn't happen, as cck should be a flip-flop and its outputs should change "sometime" after the clock edge, so any register sampling the value of cck at the same clock edge as the cck posedge transition, shouldn't see value cck=1, but cck=0.
If you take that into account, what is now a hpos 0->3 transition, should be a 0->1 transition, as bit 0 is a combinatorial of cck, and the hpos[8:1] is a flip-flop, that only sees values before its clock posedge. At the negedge of cck, which is know a 3->2 transition, should actually be a 1->2 transition - again hpos[0] is immediately going to 0, and the hpos[8:1] reg sees cck=1, so it increases its value by one.

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 Post subject: Re: Beam counter issue?
PostPosted: Thu Mar 28, 2013 3:09 pm 
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Joined: Fri Jan 20, 2012 9:32 pm
Posts: 55
chaos wrote:
Hi madeho, nice work.

Minimig is not completely cycle-exact to real hardware, so I wouldn't worry about that, unless there's a bug in some software.

Thx, I know that it isn't cycle-exact :) in a real Amiga one HPOS increments on each CCK but it also only updates bits from 8 to 1. Minimig uses 7MHz clock to increment that counter and bit 0 shall be used as a kind of prescaler. That why theoreticaly it shall count in a 'normal' way (0, 1, 2, 3, .....)
chaos wrote:
Regarding the hpos counter, it does look like something might be wrong there, as bit 0, which is a non-registered version of cck signal, toggles at the wrong time (or the +2 counter is incremented at the wrong time), that's why it's counting in that order.

Thx again, from a code I can read why it count in that strange way .... my question was more: "Is it intended to be like that or maybe it is a bug which was introduced during migration to a 7MHz clock domain?"
chaos wrote:
How are you simulating this - are you using proper CPU / chipset timings, as that would be my first guess as to what is wrong?

This is not timing simulation it is only behavioral one. I use a real Minimig modules to get a proper set of signals needed to my development. I've found this out because I needed to simulate DMA engine and I decided to use Agnus to generate all of them.


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 Post subject: Re: Beam counter issue?
PostPosted: Thu Mar 28, 2013 3:53 pm 
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Joined: Fri Jan 20, 2012 9:32 pm
Posts: 55
Hi chaos,
chaos wrote:
... cck should be a flip-flop and its outputs should change "sometime" after the clock edge

Yes, that was a real cause of that issue .... I've too much alligned in phase clk7m and cck. Now it is adjusted and works great, strange counter behavior went away :D
Thx


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beam_counter_sim.jpg
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 Post subject: Re: Beam counter issue?
PostPosted: Thu Mar 28, 2013 6:43 pm 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
Interesting finding :)
Maybe this also helps SHires mode in both 15KHz and 31KHz mode where some vertical pixel is missing.

Do you have the source code for this part?

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 Post subject: Re: Beam counter issue?
PostPosted: Tue Apr 02, 2013 5:04 pm 
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Joined: Fri Jan 20, 2012 9:32 pm
Posts: 55
boing4000 wrote:
Maybe this also helps SHires mode in both 15KHz and 31KHz mode where some vertical pixel is missing.

Can you give more details related to that issue?

boing4000 wrote:
Do you have the source code for this part?

Sure, I have it. This is a simple testbench which uses original minimig verilog modules.

Regarding beam counter issue, it is definitively closed ... it was faulty testbench setup :).


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 Post subject: Re: Beam counter issue?
PostPosted: Wed Apr 03, 2013 10:09 am 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
madeho wrote:
boing4000 wrote:
Maybe this also helps SHires mode in both 15KHz and 31KHz mode where some vertical pixel is missing.
Can you give more details related to that issue?



In Workbench 3.1 at SuperHires are missing pixel or whole missing vertical lines of window or icon edges (left or right border).
But in DosControl 4 & 6 there are all pixel/lines visible.

Maybe this is a Workbench-only matter.
I did not use any special setting, patch or screenmode. Just the built-in SHires screenmode.

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