Here is my proposed SPI protocol update.
The protocol would (mostly) consist of an address / data pairs, 8 bits of each (we don't need 8 bits of address space yet, but for compatibility reasons it's best to stick to byte transfers over the SPI bus, even though some devices support different number of bits).
The master would first write a byte address, followed by a byte data write or read. The address selects the target register, which then receives the written data, or sends its value back to the master.
There are two options how to implement "special" registers - the OSD buffer and the system DMA. In both cases two or three registers represent the DMA address counter, which act as the base (starting) address for the DMA.
First option uses another register for the data port, so you'd write to the buffer by sending address / data 16 bit transfers to this register. Downside is that the bandwidth is halved, as each byte of data for the OSD or system DMA would need a two byte transfer. The upside is that this way is fully consistent with the protocol for other registers.
Second option is to use that register as a length indicator, and after writing that register, any bytes up to length would be directly interpreted as data. The downsides / upsides are just the opposite from option one: the protocol in no longer consistent with the other registers, but you can achieve full bandwidth.
I think that even with half the bandwidth the protocol would still be fast enough, so I'd go with the first option, as that allows a smaller, cleaner implementation of the SPI communication.
Here is a list of proposed register addresses and their approximate functions:
00 - core version / ID
01 - reset control (CPU & chip, space for extensions)
02 - chip freq config (for chip PLL settings - speed etc)
03 - CPU freq config (for CPU PLL settings - speed etc)
04 - chipset config (NTSC, OCS, ECS, AGA, autofire, ...)
05 - CPU config (type, ...)
06 - memory config (chip, slow, fast, cache, ...)
07 - video config (scanlines, interpolation filter, dithering)
08 - floppy config (speed, no. of floppies)
09 - hard disk config (...)
0a - not implemented
0b - not implemented
0c - OSD control (enable, keyboard, background, ...)
0d - OSD address [15:8]
0e - OSD address [7:0]
0f - OSD buffer port (or length value)
10 - system DMA address [24:16]
11 - system DMA address [15:8]
12 - system DMA address [7:0]
13 - DMA buffer port (or length value)
Any thoughts, any missing registers?
It would be great if all different cores on all the boards would (at least try to) support the same protocol for CPU - core communications. We should agree on a base set of registers that all cores would support (like ID, PLL config, OSD and DMA). Of course, not all cores need all of these features, but we should at least try to avoid register address clashes.
BTW, I'm working on an updated C64 core which will support ROM upload and floppy emulation among other things, so I'd like to use any updated SPI protocol that we will agree upon.
** my minimig builds: http://somuch.guru/ **