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 Post subject: PONG core for MiniMig
PostPosted: Fri Jan 23, 2009 8:22 am 
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Joined: Thu Jan 15, 2009 12:41 pm
Posts: 28
Hi. I was wondering if someone has tried to port PONG source to the MiniMig. It is a free Verilog source. Here is the source in case someone wants it:

I thought it would be a nice test-program to get me going. I believe I have to assign all the pins and stuff to the right ones on the minimig in order to get vga-out to work, and to map the right pins to ps/2. Someone here who wants to help out ?

// Pong VGA game
// (c) fpga4fun.com

module pong(clk, vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B, quadA, quadB);
input clk;
output vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B;
input quadA, quadB;

wire inDisplayArea;
wire [9:0] CounterX;
wire [8:0] CounterY;

hvsync_generator syncgen(.clk(clk), .vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync),
.inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));

/////////////////////////////////////////////////////////////////
reg [8:0] PaddlePosition;
reg [2:0] quadAr, quadBr;
always @(posedge clk) quadAr <= {quadAr[1:0], quadA};
always @(posedge clk) quadBr <= {quadBr[1:0], quadB};

always @(posedge clk)
if(quadAr[2] ^ quadAr[1] ^ quadBr[2] ^ quadBr[1])
begin
if(quadAr[2] ^ quadBr[1])
begin
if(~&PaddlePosition) // make sure the value doesn't overflow
PaddlePosition <= PaddlePosition + 1;
end
else
begin
if(|PaddlePosition) // make sure the value doesn't underflow
PaddlePosition <= PaddlePosition - 1;
end
end

/////////////////////////////////////////////////////////////////
reg [9:0] ballX;
reg [8:0] ballY;
reg ball_inX, ball_inY;

always @(posedge clk)
if(ball_inX==0) ball_inX <= (CounterX==ballX) & ball_inY; else ball_inX <= !(CounterX==ballX+16);

always @(posedge clk)
if(ball_inY==0) ball_inY <= (CounterY==ballY); else ball_inY <= !(CounterY==ballY+16);

wire ball = ball_inX & ball_inY;

/////////////////////////////////////////////////////////////////
wire border = (CounterX[9:3]==0) || (CounterX[9:3]==79) || (CounterY[8:3]==0) || (CounterY[8:3]==59);
wire paddle = (CounterX>=PaddlePosition+8) && (CounterX<=PaddlePosition+120) && (CounterY[8:4]==27);
wire BouncingObject = border | paddle; // active if the border or paddle is redrawing itself

reg ResetCollision;
always @(posedge clk) ResetCollision <= (CounterY==500) & (CounterX==0); // active only once for every video frame

reg CollisionX1, CollisionX2, CollisionY1, CollisionY2;
always @(posedge clk) if(ResetCollision) CollisionX1<=0; else if(BouncingObject & (CounterX==ballX ) & (CounterY==ballY+ 8)) CollisionX1<=1;
always @(posedge clk) if(ResetCollision) CollisionX2<=0; else if(BouncingObject & (CounterX==ballX+16) & (CounterY==ballY+ 8)) CollisionX2<=1;
always @(posedge clk) if(ResetCollision) CollisionY1<=0; else if(BouncingObject & (CounterX==ballX+ 8) & (CounterY==ballY )) CollisionY1<=1;
always @(posedge clk) if(ResetCollision) CollisionY2<=0; else if(BouncingObject & (CounterX==ballX+ 8) & (CounterY==ballY+16)) CollisionY2<=1;

/////////////////////////////////////////////////////////////////
wire UpdateBallPosition = ResetCollision; // update the ball position at the same time that we reset the collision detectors

reg ball_dirX, ball_dirY;
always @(posedge clk)
if(UpdateBallPosition)
begin
if(~(CollisionX1 & CollisionX2)) // if collision on both X-sides, don't move in the X direction
begin
ballX <= ballX + (ball_dirX ? -1 : 1);
if(CollisionX2) ball_dirX <= 1; else if(CollisionX1) ball_dirX <= 0;
end

if(~(CollisionY1 & CollisionY2)) // if collision on both Y-sides, don't move in the Y direction
begin
ballY <= ballY + (ball_dirY ? -1 : 1);
if(CollisionY2) ball_dirY <= 1; else if(CollisionY1) ball_dirY <= 0;
end
end

/////////////////////////////////////////////////////////////////
wire R = BouncingObject | ball | (CounterX[3] ^ CounterY[3]);
wire G = BouncingObject | ball;
wire B = BouncingObject | ball;

reg vga_R, vga_G, vga_B;
always @(posedge clk)
begin
vga_R <= R & inDisplayArea;
vga_G <= G & inDisplayArea;
vga_B <= B & inDisplayArea;
end

endmodule


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 Post subject: Re: PONG core for MiniMig
PostPosted: Sat Jan 24, 2009 12:30 am 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
I did and it works. This was my first "porting" with visual output to the minimig board. Actually only the pinlayout .ucf had to be adapted to this core.
You can find some pictures and (german) infos here: http://www.a1k.org/forum/showpost.php?p=228447&postcount=219.
Currently an external clock is necessary. I connected the A'Nel SpeedMaker (variable digital frequence generator (for Amiga)) to Spare-I/O pin #3. Set to 25-30MHz will show some VGA like screen. In time I will create a dcm module to let this run out-of-the-box with onboard 4.433MHz clock rate.

Pong is nice but just a test. No score or lost of balls is possible... :)

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 Post subject: Re: PONG core for MiniMig
PostPosted: Sat Jan 24, 2009 12:10 pm 
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Joined: Thu Jan 15, 2009 12:41 pm
Posts: 28
I think I will have to see if I can add a internal clock gen for this source, as i do not own a clock gen to use externally. However, that should just be a cool project to try to implement, though :-)

Do you mind sharing the source project for your pong-port ?


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 Post subject: Re: PONG core for MiniMig
PostPosted: Sun Jan 25, 2009 3:00 am 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
As soon as an internal clock generation is working, I will post it here :)
Some help in this matter is still welcome.

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JMP $00000BED ; will guru-meditation until next morning


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 Post subject: Re: PONG core for MiniMig
PostPosted: Sun Jan 25, 2009 4:20 pm 
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Joined: Mon Dec 01, 2008 10:11 am
Posts: 197
Hi guys,

I have prepared a top hierarchy Minimig source file which demonstrates use of DCM module.

As an example I used Pong Game from fpga4fun.com. Please visit http://www.fpga4fun.com/PongGame.html for details and necessary source files. Binary FPGA core file is included in the attachment.

For those who want to use a DCM in their own designs: please keep in mind that a DCM working in frequency synthesis mode cannot output signal lower than 18 MHz (in case of Spartan3). If you need such a signal you have to use another DCM working in DDL mode to divide the output frequency of the first DCM (see Minimig source files).


Attachments:
File comment: Pong Game from fpga4fun.com ported to Minimig
minipong.zip [9.59 KiB]
Downloaded 369 times
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 Post subject: Re: PONG core for MiniMig
PostPosted: Sun Jan 25, 2009 6:36 pm 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
Hi Jakub,

thank you, thats very nice :)
Until now I was not able to use some self made DCM. The output frequence sometimes was even lower than input one. This raw model will certainly help!
The binary is working fine and with native Amiga mouse some feeling of Arkanoid or Crystal Hammer is coming up :D

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JMP $00000BED ; will guru-meditation until next morning


Last edited by boing4000 on Sun Jan 25, 2009 7:28 pm, edited 1 time in total.

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 Post subject: Re: PONG core for MiniMig
PostPosted: Sun Jan 25, 2009 7:04 pm 
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Joined: Sat Jan 17, 2009 10:13 pm
Posts: 106
Works :D

Image

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proud owner of selfmade minimig and ARM kit :D


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 Post subject: Re: PONG core for MiniMig
PostPosted: Mon Jan 26, 2009 7:54 am 
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Joined: Thu Jan 15, 2009 12:41 pm
Posts: 28
Hey, it is really cool to see how these fpga topics develop and how many ppl there are who find it interesting. Hopefully, even more ppl with get their eyes up for this and joins this forum.

BTW: Anyone here who knows if there has been any leaking of the c64DTV core somewhat ? Maybe to the C-ONE ? I fancy those new features of the DTV_V3. Would be nice to see it on the minimig board aswell.

Espen


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