It's verilog not vhdl
Don't try to synthesis with the sim_* files, as the README mention, they are there only for simulation in iverilog,
just start from minimigmac.v as your toplevel and add the missing bits the parser requires
You also need only clocks_fpga.v, ignore clocks_fpga_dll.v for now
There should be pre-built binaries of the fpga and the PIC in the 0.1 archive I've posted in the builds directory.
As for rebuilding the .hex if you don't like the binary, it's meant to build with "sdcc" which is available under Linux
and most probably other platforms (Google....). There's a quick & dirty Makefile in there.