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 Post subject: FAST RAM: impossible on the V1.1 board?
PostPosted: Wed Apr 24, 2013 7:04 pm 
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Joined: Thu Jun 18, 2009 9:54 am
Posts: 349
Hi there, boing4000 & cia!

I was playing some Lucas Arts games on the DE1 the other day and noticed how great they run on the Minimig core on that board. They run perfect! Fast, smooth and zero skipping samples. Beautiful!

However, to get the same degree of perfection on the V1.1 board (wich is an Amiga 500-like computer anyway) it must be set at 50Mhz TURBO CPU speed, wich causes skipped notes in Monkey Island and lockups in Loom.

So, what makes the DE1 port so smooth and fast with zero errors or skipped notes? DE1 runs on an apox. 7Mhz TG68 softcore after all.
Well, the answer is FAST RAM instead of SLOW RAM. (Now this idiot has discovered the wheel, you must be thinking! :D)

My question is: would it be physicall possible to have FAST RAM instead of SLOW RAM on the V1.1 board? I read RAM access on the Minimig is multiplexed between CPU and chipset, so I suspect it's physically impossible to disable SLOW RAM and have FAST RAM instead, but well, I wanted to know for sure :)

Thanks!


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 Post subject: Re: FAST RAM: impossible on the V1.1 board?
PostPosted: Wed Apr 24, 2013 7:21 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
Maybe I can add something:

The SDRAM on the DE1 board is also shared between the CPU, the custom chips and the fastRAM access, and the same thing could be implemented on the original minimig by replacing slow ram with fast ram ...

... BUT it would not run as fast as on the DE1 & other boards with SDRAM, because the SDRAM controller runs at a very high clock (~117MHz) and uses a SDRAM feature called burst read, which means it reads data from four consecutive addresses in rapid succession (that is in just four clocks), and then uses cache to save that data for later accesses.

So you could have fastRAM on the original minimig, but it would be fastRAM just by name and memory address, and not by speed, unfortunately. You could speed it up somewhat by implementing cache for it, but the speedup would probably be small.

Sorry to crush your hopes :S, but I think the minimig as it is, is still one of the best A500 implementations available.

EDIT: on the bright side, turbo mode only works on the original minimig board, AFAIK ;)

@boing4000: do you have any insights into the turbo mode requirements? Shouldn't it work without increasing the CPU frequency? I tried to implement it on the DE1 board, and the system gets completely unstable if I just enable turbo for the Agnus, without increasing the CPU frequency. After looking at the code, it seems all it does is allow extra slots for chip DMA, which is what I want, but like I said, it doesn't work.

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 Post subject: Re: FAST RAM: impossible on the V1.1 board?
PostPosted: Thu Apr 25, 2013 12:43 pm 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
Real fastram is not possible for the MinimigV1 board.
This is due to only one available bus to all S-RAM chips.

Chipset DMA will always slow down any access, so the addressed $C00000 RAM automatically is slow as chipram by nature.
To make real fastram, an own/independent address and data bus would be necessary.
This is not possible to do on the V1 board, since there is no room and no free FPGA pin available.

At Turbo mode the chip- and slow RAM is faster than in original Amiga.
Its about twice as fast and together with the 4KB cpu cache, the system is speed-up a lot.
But this may cause some title to show problems because the cache really is fast with zero waitstate ;)

But there is a way to disable the Cache: Set Scanlines to BLK/BLANK.
In this case the cpu is forced to access ram and should be a lot slower.

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 Post subject: Re: FAST RAM: impossible on the V1.1 board?
PostPosted: Thu Apr 25, 2013 1:03 pm 
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Location: .de
chaos wrote:
@boing4000: do you have any insights into the turbo mode requirements? Shouldn't it work without increasing the CPU frequency? I tried to implement it on the DE1 board, and the system gets completely unstable if I just enable turbo for the Agnus, without increasing the CPU frequency. After looking at the code, it seems all it does is allow extra slots for chip DMA, which is what I want, but like I said, it doesn't work.


Im sorry, I don't have any experience in Minimig running on boards using TG68k core.

The Turbo function in Agnus is called "fast chip" and only should disable Blitter slowdown and allow more DMA channel for Floppy data transfer. This was in general also present in the very first release by Dennis van Weeren.
But I can not help out for the DE1 board.

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 Post subject: Re: FAST RAM: impossible on the V1.1 board?
PostPosted: Thu Apr 25, 2013 1:42 pm 
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Joined: Tue Dec 13, 2011 7:48 pm
Posts: 341
chaos wrote:
@boing4000: do you have any insights into the turbo mode requirements? Shouldn't it work without increasing the CPU frequency? I tried to implement it on the DE1 board, and the system gets completely unstable if I just enable turbo for the Agnus, without increasing the CPU frequency. After looking at the code, it seems all it does is allow extra slots for chip DMA, which is what I want, but like I said, it doesn't work.


I tried that on the Chameleon but couldn't get it working at all - the system wouldn't even boot. Are you saying that it boots but crashes at the drop of a hat? If so, check the SDRAM refresh - On the Chameleon I ended up adding a counter for memory refresh, and giving it priority over Fast RAM. The original SDRAM controller for the Chameleon core just devoted any idle RAM slots to refresh and assumed there'd be enough of them to keep the RAM refreshed.

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 Post subject: Re: FAST RAM: impossible on the V1.1 board?
PostPosted: Thu Apr 25, 2013 10:45 pm 
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MMrobinsonb5 wrote:
I tried that on the Chameleon but couldn't get it working at all - the system wouldn't even boot. Are you saying that it boots but crashes at the drop of a hat? If so, check the SDRAM refresh - On the Chameleon I ended up adding a counter for memory refresh, and giving it priority over Fast RAM. The original SDRAM controller for the Chameleon core just devoted any idle RAM slots to refresh and assumed there'd be enough of them to keep the RAM refreshed.

Ah OK, thanks. I did notice that the refresh slot was given lowest priority, so I moved it above host slot, but that is not used on the DE1 anyway. That could be the reason why turbo mode doesn't work, it seems it requires faster memory accesses, as mentioned by boing4000. Something worth looking into, I guess.

Good idea adding the refresh counter! The SDRAM autorefresh is a nice feature, since it only requires that all the lines get refreshed in a certain time period, but not the specific time of the refresh cycle, so a little logic combined with a refresh counter allows you to schedule priority accesses (chip) before the refresh even if the counter is at zero, your logic just needs to 'remember' that and schedule a refresh just after priority access. Of course, if there are too many priority accesses (and no backpressure control), this will not work. Unfortunately, there's no backpressure control (like an ack signal) for the chip acccesses ...

The SDRAM controller will have to be rewritten for AGA anyway (not something I look forward to :)), hopefully there will be enough bandwidth (and small delays) to make it work for 64bit transfers, which I still haven't figured out. But the rest of AGA logic seems pretty doable, I think - already have some parts working, as I found a nice document describing the changes (aga guide).

Oh BTW, MMrobinsonb5: I have some links & documentation for RTG, if you are interested?

@gaula92: sorry for hijacking your thread :) This kind of discussions should really be moved to the Development section ...

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 Post subject: Re: FAST RAM: impossible on the V1.1 board?
PostPosted: Fri Apr 26, 2013 9:05 am 
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MMrobinsonb5 wrote:
it seems it requires faster memory accesses, as mentioned by boing4000. Something worth looking into, I guess.

At least for the MinimigV1 board, the RAM access speed itself do not change.
RAM is always clocked at the same speed, no matter if Normal or Turbo mode is active.

But S-RAM require no refresh cycle and I don't have any knowledge about SD-RAM handling.

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 Post subject: Re: FAST RAM: impossible on the V1.1 board?
PostPosted: Fri Apr 26, 2013 11:27 am 
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Joined: Tue Dec 13, 2011 7:48 pm
Posts: 341
chaos wrote:
The SDRAM controller will have to be rewritten for AGA anyway (not something I look forward to :)), hopefully there will be enough bandwidth (and small delays) to make it work for 64bit transfers, which I still haven't figured out.


There's definitely enough bandwidth for 64-bit transfers, because the SDRAM controller's already using 64-bit bursts, and for chip cycles it's discarding 48 of them! We only have to worry about 64-bit reads, too, not writes, since only the bitplane hardware (and sprites?) makes use of the extra bandwidth. Latency might be an issue, but I'm hoping not.

Quote:
Oh BTW, MMrobinsonb5: I have some links & documentation for RTG, if you are interested?


Most definitely!

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Details of my projects: http://retroramblings.net


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