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Discussing the Open Source FPGA Amiga Project
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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 4:09 pm 
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Posts: 55
boing4000 wrote:
Im sorry but your cores do not work.
The "potinp_test" show a static POTGO: $0000, POTINP: $5500 at the last line of bootloader


Did you try to press 2nd FB of joy2 or middle (3rd) button of mouse? When you will press joystick button you will see changes in a POTINP data, when you will press middle mouse button POTGO data shall change (every press will increase potgo reg by $4000). additionally pressing rmb and middle buttun will also affect potinp register on bit 10 and 8 just like in HRM

boing4000 wrote:
OSD flicker/appear at random.

How is autofire controlled? Is a repetition rate setup from OSD? Maybe that cause that OSD appear in random way?

boing4000 wrote:
Im sorry but your cores do not work.
Real MINIMIG V1.1 board has hardware differences to any other Amiga hardware board.
Please take a look at the Schematics if you do not believe me.

Once again I will ask "what are that differences except of charge capacitor?". This is the only one according to a pin 5 and 9 of joystick connector. I shall be even a plus for us because we dont need to wait until capacitor will charge.


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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 6:32 pm 
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Posts: 1568
Location: .de
It seems you did not define JOY pins with a pull-up in .ucf file.
Because OSD and joystick signal flicker arround by only touching the joystick or port pins.

The potinp core do not show any action to any joy or mouse signal.

Once again I will describe it:
Minimig V1 board has static hard-wired hard-solder OUT pins to system GND (0V). There is no programming via POTGO possible like in original Amiga hardware.

I dont know what hardware you have for testing but this all is not working on the Minimig V1 board.
Also a global working fix for those games is not possible.
Final solution: Asterix will stay out to let most other games work :)

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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 7:10 pm 
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Posts: 55
After hours spent on looking for an OSD flickering issue finally I've found second file where I messed up a little.
boing4000 wrote:
It seems you did not define JOY pins with a pull-up in .ucf file.

Yes ... that is what I found out.

boing4000 wrote:
Minimig V1 board has hard wired/solder OUT pins to system GND (0V), so there is no programming possible like in original Amiga hardware.

Which one pins exactly ... just write a names. There are only 4 pins 'connected' to a POTINP register:
1) POT1Y connected to a RIGHT JOY connector pin9 through series resistor (just like a minimig board),
2) POT1X connected to a RIGHT JOY connector pin5 through series resistor (not available in minimig, connector pin left open),
3) POT0Y connected to a LEFT JOY connector pin9 through series resistor (just like a minimig board),
4) POT0X connected to a LEFT JOY connector pin5 through series resistor (not available in minimig, connector pin left open),
None of them is wired/soldered to GND

boing4000 wrote:
I dont know what hardware you have for testing but this all is not working on the Minimig V1 board.

Any HW which have Spartan FPGA w/ a a user available pin and series resistor between them

Going back on track ... now, it should finally works. There are 2 files: minimig - to test a feature in a "real" life (asterix and SSF2 games) and there is also potinp_test file to show that IO port from paula can be replicated.

According to a second file, state of POTGO, POTINP JOY0DAT and JOY1DAT will be displayed. To change paula port settings you have to press left mouse button. On a high part of POTINP register states of a lines POT1Y, POT1X, POT0Y and POT0X will be shown (just like it shall be according to HRM) low byte of that register will show as follow (from bit 7 to 0): _fire0, joy2enable, _xjoy2[5:0] signal states. When left button is pressed background shall change color an power led shall be off. after button release background color shall return to a previous one and led shall be on again
To test a solution set different configurations for port and in each of them test behavior of a joy2 2nd fire button (bit14 in POTINP register)

Have fun :). When it will finally works I will also add sources for that fix.


Attachments:
potinp_test.zip [97.82 KiB]
Downloaded 101 times
minimig1.zip [98.38 KiB]
Downloaded 110 times
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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 9:18 pm 
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Joined: Mon Dec 01, 2008 9:58 pm
Posts: 1568
Location: .de
My fault: The pins #5 of both JOY ports are OPEN, not wired-up at all.
So they are not grounded but also not programmable. Sorry, I mixed this up.
Nevertheless this pins can not response as programed to its input counterpart.

Your core binary "minimig1" is working now, OSD and joy ports do not flicker.
But Asterix game can not read right mouse button (RMB) as expected to be honest!
Even if it works, other games will not work right.

This is because the game read whole POTGOR register and compare its value to a static bit pattern to detect RMB is pressed. This bit pattern will only appear by ANDing POTINP with POTGO register bits. Its the only working solution for Asterix.
But this will cause trouble for other games, as reported.

The "test" core now show all register value by moving joystick and pressing buttons.
Looks nice but will no help in this matter.

I spend a lot of time and found no global working solution.
The only one was: No Asterix support.

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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 9:25 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
boing4000: as for all I know, even real Amigas had problems with some game / kickstart combinations regarding handling of the second button, so nothing new here :)

But there is nothing in real Amigas that the minimig couldn't reproduce, even the external capacitor could be simulated inside the FPGA if needed. I think I might have a working solution, I'm testing it now.

So the games to test are mainly Asterix & SSF2?

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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 10:00 pm 
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Joined: Fri Jan 20, 2012 9:32 pm
Posts: 55
boing4000 wrote:
My failt: The pins #5 of both JOY ports are OPEN, not wired-up at all.
So they are not grounded but also not programmable. Sorry, I mixed this up.
Nevertheless this pins can not response as programed to its input counterpart.

Now I can agree :) ... but pin#5 is used as a middle mouse button only so it will be usually open. and it shouldn't be issue.

boing4000 wrote:
But Asterix game can not read right mouse button (RMB) as expected to be honest!

Have you try it? RMB and 2FB shall works w/o any issues.

boing4000 wrote:
This is because the game read whole POTGOR register and compare its value to a static bit pattern to detect RMB is pressed.

This design simulate all 4 pins. As long as you don't expect anything on pin#5 everything should be ok. state of a POTINP will be dependent from that what was written to a POTGO register and states of pins#9. pins5 will always be reported as '1' unless you will configure them to be an output and set them to a '0'. Then POTINP shall report a state as a '0'.
Can you give me example what is written to POTGO register and what is expexted to get from POTINP in Asterix?

boing4000 wrote:
But this will cause trouble for other games, as reported.

As long as they will not check middle mouse button or use POT0DAT and POT1DAT all should works fine

boing4000 wrote:
The "test" core now show all register value by moving joystick and pressing buttons.
Looks nice but will no help in this matter.

Didi you try to change POTGO register values (clicking LMB)? If you do that you will be able to test all 4 possible configurations for pin and read its value from POTINP register. 3 other pins behave the same

As I said, when it start works I will add sources for that .... enjoy.


Attachments:
paula_port_fix.zip [22.13 KiB]
Downloaded 112 times
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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 10:11 pm 
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Joined: Fri Jan 20, 2012 9:32 pm
Posts: 55
chaos wrote:
boing4000: as for all I know, even real Amigas had problems with some game / kickstart combinations regarding handling of the second button, so nothing new here :)

But there is nothing in real Amigas that the minimig couldn't reproduce, even the external capacitor could be simulated inside the FPGA if needed. I think I might have a working solution, I'm testing it now.

So the games to test are mainly Asterix & SSF2?


Can you conduct some test of my core w/ Asterix & SSF2 games? I'm really curious how they will behave.
Thx in advance :)


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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 10:17 pm 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
madeho: I'm sorry, I don't have a minimig board, I'm working on the DE1 board, otherwise I would test your cores.

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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Wed Mar 20, 2013 10:25 pm 
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Joined: Fri Jan 20, 2012 9:32 pm
Posts: 55
chaos wrote:
madeho: I'm sorry, I don't have a minimig board, I'm working on the DE1 board, otherwise I would test your cores.

OK, I understand. In my last post I've attached updated sources you can use them to build DE image


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 Post subject: Re: Minimig FSB130117 FPGA core
PostPosted: Thu Mar 21, 2013 12:36 am 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 316
OK, I have some good results at least in Asterix and SSF2, i'll try some more games tomorrow. I won't attach the changed Userio.v as the version used in DE1 is somewhat different, but here are the changed sections, if someone wants to try:

Code:
// UPDATE THIS PART IF NECESSARY
// POTGO register
always @(posedge clk)
  if (reset)
    potreg <= 0;
  else if (reg_address_in[8:1]==POTGO[8:1])
    potreg[15:0] <= data_in[15:0];

// ADD THIS PART
// potcap reg
reg  [4-1:0] potcap;
always @ (posedge clk) begin
  if (reset)
    potcap <= 4'h0;
  else begin
    if (!_sjoy2[5]) potcap[3] <= 1'b0;
    else if (potreg[15] & potreg[14]) potcap[3] <= 1'b1;
    if (!1'b1) potcap[2] <= 1'b0;
    else if (potreg[13] & potreg[12]) potcap[2] <= 1'b1;
    if (!(_mright&_sjoy1[5]&_rmb)) potcap[1] <= 1'b0;
    else if (potreg[11] & potreg[10]) potcap[1] <= 1'b1;
    if (!_mthird) potcap[0] <= #1 1'b0;
    else if (potreg[ 9] & potreg[ 8]) potcap[0] <= 1'b1;
  end
end

// UPDATE THIS PART
//data output multiplexer
always @(*)
   if ((reg_address_in[8:1]==JOY0DAT[8:1]) && joy1enable)//read port 1 joystick
      data_out[15:0] = {6'b000000,~_sjoy1[1],_sjoy1[3]^_sjoy1[1],6'b000000,~_sjoy1[0],_sjoy1[2]^_sjoy1[0]};
   else if (reg_address_in[8:1]==JOY0DAT[8:1])//read port 1 mouse
      data_out[15:0] = mouse0dat[15:0];
   else if (reg_address_in[8:1]==JOY1DAT[8:1])//read port 2 joystick
      data_out[15:0] = {6'b000000,~_sjoy2[1],_sjoy2[3]^_sjoy2[1],6'b000000,~_sjoy2[0],_sjoy2[2]^_sjoy2[0]};
   else if (reg_address_in[8:1]==POTINP[8:1])//read mouse and joysticks extra buttons
      data_out[15:0] = {1'b0, potcap[3], 1'b0, potcap[2], 1'b0, potcap[1], 1'b0, potcap[0], 8'h00};

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