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Discussing the Open Source FPGA Amiga Project
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 Post subject: Port to Nexys4Video board
PostPosted: Tue Nov 21, 2017 12:44 am 

Joined: Mon Nov 20, 2017 3:26 pm
Posts: 2
Hi, I'd like to try porting Minimig to the Nexys4 Video board.

Where's the best place to start ? Is there a zip file with RTL code somewhere ?

I'm mainly interested in getting text output and keyboard input working first. I plan to turn it into a multi-core machine.

 Post subject: Re: Port to Nexys4Video board
PostPosted: Wed Nov 22, 2017 1:03 pm 

Joined: Mon Nov 20, 2017 3:26 pm
Posts: 2
After a hectic day and a half of porting it doesn't work - yet.

I started a port of Minimig to the NexysVideo board. I found a version of Minimig to start with (the original I think). I had to re-write the clock module to make use of the 100 MHz source clock on the board. And alter the clocks used in the system. A top level module was created and the TG68 core, an RGB2DVI converter core, and sync generator core added. I’ve also decided to go for a 640x768 display, rather than 640x512. Currently the screen comes up blank and I was expecting a menu. It looks like the cpu isn’t booting properly. (The low abits are all fixed at ones). The system is probably clocking properly because the monitor reports the display resolution as 1280x768.

Clock Calculation: (based on 1280x768 display).
1680 total horizontal clocks @80MHz for 1280x768 display.
Why ? 80MHz = 1/5 of 400MHz, 400MHz = DDR3 clock rate, reused for RGB2DVI converter.
227 horizontal positions (bus clocks) for the Amiga display (one scan line)
To get 640 displayed pixels per scan line in NTSC, the pixel rate has got to be about 16MHz.
640 pixels = ½ of 1280, so the pixel clock rate needs to be ½ 80 MHz = 40 MHz. Minimig original uses a 28MHz clock rate.
1680/227 = 7.4 (ratio of video to bus clocks).
For the ideal bus rate the clock rate has to be 7.4 times lower than the clock rate for 1680.
So the bus clock rate needs to be 80MHz / 7.4 = 10.8 MHz (vs 3.58MHz base rate). This is roughly 3x the Amiga rate which makes sense because the horizontal frequency for 1280x768 mode is about 3x that of an NTSC display (15750).
In order to keep all the clock edges synchronous it’s probably better to use 10 MHz.
At a 10MHz rate only 1680/8 = 210 bus cycles.
To get to 227 horizontal positions 17 more bus clocks are needed, which is 17*8 + 1680 = 1816 total for the scanline. But hopefully we can live with 210 bus cycles.
*Audio DMA would be occurring at 3x the normal rate. May have to limit audio dma to every third scanline.

There are 768 scanline this is 1/3 more than 512 scanlines in a 640x512 display. The total number of vertical lines has to be increased in order to get the sync rate close to 60Hz.

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