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Discussing the Open Source FPGA Amiga Project
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 Post subject: YACHT
PostPosted: Sun Jun 24, 2012 8:42 pm 
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Joined: Sun Jun 24, 2012 5:03 am
Posts: 4
Yet (another) Amiga Compatible Hardware Threat

While still active in the last 25 years for AMIGA, Video and digital Television I will announce that I will start with an own minimig like hardware platform with the following features:

- FPGA hardware based on state of the art technics:
- Xilinx Spartan6
- DDR 3 Memory
- HD capable DVI-D/HDMI videoout(and audio) with upscaling

While I devoped a lot of Genlocks, I will provide genlock functionality:
- Build-In genlock, running in HD resolution
- Build-In videomixer with Timebasecorrector for providing tricks for up to 3 videosources

Since minimig have seen a bunch of iterations of "external intelligence" in form of PICs, ARM, Soft-68000 and Opencores-RISC at last, I will add the next variation:
- ARM Cortex with integrated MPEG Decoding support (MPEG2 & H.264), sATA, Highspeed SD-Card
- Eventually Usage of Linux or Android with Touch Screen Control

Last, not least, at least two DVB-Receivers should be added to get the new "amiga" to be used every day (by consuming television)...

I would be happy to find active Co -worker, aspecially for all arm (software stuff)...

Best regards

Bergy


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 Post subject: Re: YACHT
PostPosted: Mon Jun 06, 2016 8:00 am 
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Joined: Sun Jun 24, 2012 5:03 am
Posts: 4
Unfortunately I did not get any response to my offer done more or less exactly four years ago.
While no further announcement on YACHT could be found, it appears that YACHT might mayfly?

Not necessary, some of the pointed features, I´ve had made years ago (I had made commercial genlocks in the good all AMIGA days), I also implemented HDMI Videooutputs (only partly without that grapy HDCP protection), DDR type memories on a variety of different FPGA families. Also done some DVB based peripheral.
In the last years I were very busy with providing hardware platforms for ARM CPUs (not the ARM-SOC FPGAs itself) but even for “real” ARM CPU and SOC development and a bunch of ARM based Embedded Platforms of different vendors.

I will now restart the project. Since it seems that there are not many people realy looking for the descripted features, I will not focus any more on a ready to run hardware but will focus to push the Minimig Project at all.

I will provide some details in the next days.

I would be very happy, if there are still people interessted and active to the Minimig and willing to discuss different aspects of my work.

Best Regards

Bergy


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 Post subject: Re: YACHT
PostPosted: Thu Jul 21, 2016 10:57 am 
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Joined: Tue Nov 09, 2010 3:10 pm
Posts: 312
Hi,

I guess I'm interested, depends on what you are planning to do / work on. Please describe what exactly are you trying to do.

_________________
** my minimig builds: http://somuch.guru/ **


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 Post subject: Re: YACHT
PostPosted: Fri Jul 22, 2016 6:01 am 
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Joined: Sun Jun 24, 2012 5:03 am
Posts: 4
chaos wrote:
I guess I'm interested, depends on what you are planning to do / work on. Please describe what exactly are you trying to do.


Hi chaos,

At this point only a list of my actions, more detailed plans andd documentation for the things already done:

Do code rework to allow Synthesis with different tools without errors and less warnings (Modelsim, ActiveHDL, ISE/Vivado) based on a refork of the minimig-mist - Last I found a nasty bug (wrong or incomplete error-message) a few days ago on QuartusII and could now resynthesize a working firmware for Minimig-Mist - so almost DONE

Made some changes in TG68 to eleminate unwanted latches - DONE, Tests in progress

Translate TG 68 to Verilog + Code Optimisations to allow Mhz++ - Planned

Minimig SPI Interface lis imited to somewhat 20Mhz - Will recode them to allow higher clockrates - Planned

Simulation of the complete Minimig-Core with Icarus (free Verilog Simulator) - Planned

Provide an FMC-PCB with Video-Output, ARM-uC, SD Card, Joystickports and optional RAM to allow Ports to all kind of Xilinx-Evalboards (propably also Lattice and Altera (Third-Party Only)) - Sceduled for this year

Write an generic DDR3 Core to run Mininimg on different actual FPGA Eval Boards (Altera + Xilinx) - Planned

Built an FPGA Daughter Board for Raspberry PI (propably others with same IO-Connector Pinout) plus Provide AMIGA Videoout via CSI Interface to provide VideoThrough



Backport the design to Xilinx - Have to make some changes for testing it on an Kintex Board with Pseudo Static RAM (planned for the next days)


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